[PATCH] drm/amdgpu: Added check for RAS EEPROM support

From: "Clements, John" <John.Clements@amd.com>
To: "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>,
	"Zhang, Hawking" <Hawking.Zhang@amd.com>
Subject: [PATCH] drm/amdgpu: Added check for RAS EEPROM support
Date: Fri, 17 Jan 2020 09:43:10 +0000	[thread overview]
Message-ID: <MN2PR12MB366303B43AA493B2893B8922FB310@MN2PR12MB3663.namprd12.prod.outlook.com> (raw)


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[AMD Official Use Only - Internal Distribution Only]

Submitting patch to disable access of RAS EEPROM in event SMU is disabled during modprobe phase.

Thank you,
John Clements

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From 08b748fb739574a6fa82121086c2b878cd443bd6 Mon Sep 17 00:00:00 2001
From: John Clements <john.clements@amd.com>
Date: Fri, 17 Jan 2020 17:39:31 +0800
Subject: [PATCH] drm/amdgpu: Added check for RAS EEPROM support

If SMU is disabled prevent access to RAS EEPROM

Change-Id: I26b4a265235b246eb860dd9c4000860d61a3b21f
Signed-off-by: John Clements <john.clements@amd.com>
---
 .../gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c    | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index 2a8e04895595..4e4c03f62697 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -174,12 +174,29 @@ static bool __validate_tbl_checksum(struct amdgpu_ras_eeprom_control *control,
 	return true;
 }
 
+static bool __is_eeprom_supported(struct amdgpu_ras_eeprom_control *control)
+{
+	struct amdgpu_device *adev = to_amdgpu_device(control);
+	struct amdgpu_ip_block *smu_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC);
+
+	if (!smu_block || !smu_block->status.valid)
+	{
+		DRM_WARN("SMU disabled, RAS EEPROM not supported\n");
+		return false;
+	}
+
+	return true;
+}
+
 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control)
 {
 	unsigned char buff[EEPROM_ADDRESS_SIZE + EEPROM_TABLE_HEADER_SIZE] = { 0 };
 	struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr;
 	int ret = 0;
 
+	if (!__is_eeprom_supported(control))
+		return 0;
+
 	mutex_lock(&control->tbl_mutex);
 
 	hdr->header = EEPROM_TABLE_HDR_VAL;
@@ -212,6 +229,9 @@ int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control)
 			.buf	= buff,
 	};
 
+	if (!__is_eeprom_supported(control))
+		return 0;
+
 	mutex_init(&control->tbl_mutex);
 
 	switch (adev->asic_type) {
@@ -267,6 +287,9 @@ void amdgpu_ras_eeprom_fini(struct amdgpu_ras_eeprom_control *control)
 {
 	struct amdgpu_device *adev = to_amdgpu_device(control);
 
+	if (!__is_eeprom_supported(control))
+		return;
+
 	switch (adev->asic_type) {
 	case CHIP_VEGA20:
 		smu_v11_0_i2c_eeprom_control_fini(&control->eeprom_accessor);
-- 
2.17.1


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