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boundary="===============1481129061==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============1481129061== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB4488352EC87790ED63228C0BF7950MN2PR12MB4488namp_" --_000_MN2PR12MB4488352EC87790ED63228C0BF7950MN2PR12MB4488namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] Series is: Acked-by: Alex Deucher ________________________________ From: amd-gfx on behalf of Likun Ga= o Sent: Wednesday, June 24, 2020 2:35 AM To: amd-gfx@lists.freedesktop.org Cc: Gao, Likun ; Feng, Kenneth ; Z= hang, Hawking Subject: [PATCH 1/2] drm/amd/powerplay: change method to set board paramete= rs From: Likun Gao Copy board parameters directly instead of set each parameter for sienna_cichlid. Signed-off-by: Likun Gao --- .../drm/amd/powerplay/sienna_cichlid_ppt.c | 89 +------------------ 1 file changed, 2 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/g= pu/drm/amd/powerplay/sienna_cichlid_ppt.c index 769e031d489a..693ad8963d0a 100644 --- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c @@ -394,7 +394,6 @@ static int sienna_cichlid_append_powerplay_table(struct= smu_context *smu) PPTable_t *smc_pptable =3D table_context->driver_pptable; struct atom_smc_dpm_info_v4_9 *smc_dpm_table; int index, ret; - int i; index =3D get_index_into_master_table(atom_master_list_of_data_tab= les_v2_1, smc_dpm_info); @@ -405,92 +404,8 @@ static int sienna_cichlid_append_powerplay_table(struc= t smu_context *smu) return ret; memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers, - sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS); - - /* SVI2 Board Parameters */ - smc_pptable->VddGfxVrMapping =3D smc_dpm_table->VddGfxVrMapping; - smc_pptable->VddSocVrMapping =3D smc_dpm_table->VddSocVrMapping; - smc_pptable->VddMem0VrMapping =3D smc_dpm_table->VddMem0VrMapping; - smc_pptable->VddMem1VrMapping =3D smc_dpm_table->VddMem1VrMapping; - smc_pptable->GfxUlvPhaseSheddingMask =3D smc_dpm_table->GfxUlvPhase= SheddingMask; - smc_pptable->SocUlvPhaseSheddingMask =3D smc_dpm_table->SocUlvPhase= SheddingMask; - smc_pptable->VddciUlvPhaseSheddingMask =3D smc_dpm_table->VddciUlvP= haseSheddingMask; - smc_pptable->MvddUlvPhaseSheddingMask =3D smc_dpm_table->MvddUlvPha= seSheddingMask; - - /* Telemetry Settings */ - smc_pptable->GfxMaxCurrent =3D smc_dpm_table->GfxMaxCurrent; - smc_pptable->GfxOffset =3D smc_dpm_table->GfxOffset; - smc_pptable->Padding_TelemetryGfx =3D smc_dpm_table->Padding_Teleme= tryGfx; - smc_pptable->SocMaxCurrent =3D smc_dpm_table->SocMaxCurrent; - smc_pptable->SocOffset =3D smc_dpm_table->SocOffset; - smc_pptable->Padding_TelemetrySoc =3D smc_dpm_table->Padding_Teleme= trySoc; - smc_pptable->Mem0MaxCurrent =3D smc_dpm_table->Mem0MaxCurrent; - smc_pptable->Mem0Offset =3D smc_dpm_table->Mem0Offset; - smc_pptable->Padding_TelemetryMem0 =3D smc_dpm_table->Padding_Telem= etryMem0; - smc_pptable->Mem1MaxCurrent =3D smc_dpm_table->Mem1MaxCurrent; - smc_pptable->Mem1Offset =3D smc_dpm_table->Mem1Offset; - smc_pptable->Padding_TelemetryMem1 =3D smc_dpm_table->Padding_Telem= etryMem1; - smc_pptable->MvddRatio =3D smc_dpm_table->MvddRatio; - - /* GPIO Settings */ - smc_pptable->AcDcGpio =3D smc_dpm_table->AcDcGpio; - smc_pptable->AcDcPolarity =3D smc_dpm_table->AcDcPolarity; - smc_pptable->VR0HotGpio =3D smc_dpm_table->VR0HotGpio; - smc_pptable->VR0HotPolarity =3D smc_dpm_table->VR0HotPolarity; - smc_pptable->VR1HotGpio =3D smc_dpm_table->VR1HotGpio; - smc_pptable->VR1HotPolarity =3D smc_dpm_table->VR1HotPolarity; - smc_pptable->GthrGpio =3D smc_dpm_table->GthrGpio; - smc_pptable->GthrPolarity =3D smc_dpm_table->GthrPolarity; - - /* LED Display Settings */ - smc_pptable->LedPin0 =3D smc_dpm_table->LedPin0; - smc_pptable->LedPin1 =3D smc_dpm_table->LedPin1; - smc_pptable->LedPin2 =3D smc_dpm_table->LedPin2; - smc_pptable->LedEnableMask =3D smc_dpm_table->LedEnableMask; - smc_pptable->LedPcie =3D smc_dpm_table->LedPcie; - smc_pptable->LedError =3D smc_dpm_table->LedError; - smc_pptable->LedSpare1[0] =3D smc_dpm_table->LedSpare1[0]; - smc_pptable->LedSpare1[1] =3D smc_dpm_table->LedSpare1[1]; - - /* GFXCLK PLL Spread Spectrum */ - smc_pptable->PllGfxclkSpreadEnabled =3D smc_dpm_table->PllGfxclkSpr= eadEnabled; - smc_pptable->PllGfxclkSpreadPercent =3D smc_dpm_table->PllGfxclkSpr= eadPercent; - smc_pptable->PllGfxclkSpreadFreq =3D smc_dpm_table->PllGfxclkSpread= Freq; - - /* GFXCLK DFLL Spread Spectrum */ - smc_pptable->DfllGfxclkSpreadEnabled =3D smc_dpm_table->DfllGfxclkS= preadEnabled; - smc_pptable->DfllGfxclkSpreadPercent =3D smc_dpm_table->DfllGfxclkS= preadPercent; - smc_pptable->DfllGfxclkSpreadFreq =3D smc_dpm_table->DfllGfxclkSpre= adFreq; - - /* UCLK Spread Spectrum */ - smc_pptable->UclkSpreadEnabled =3D smc_dpm_table->UclkSpreadEnabled= ; - smc_pptable->UclkSpreadPercent =3D smc_dpm_table->UclkSpreadPercent= ; - smc_pptable->UclkSpreadFreq =3D smc_dpm_table->UclkSpreadFreq; - - /* FCLK Spred Spectrum */ - smc_pptable->FclkSpreadEnabled =3D smc_dpm_table->FclkSpreadEnabled= ; - smc_pptable->FclkSpreadPercent =3D smc_dpm_table->FclkSpreadPercent= ; - smc_pptable->FclkSpreadFreq =3D smc_dpm_table->FclkSpreadFreq; - - /* Memory Config */ - smc_pptable->MemoryChannelEnabled =3D smc_dpm_table->MemoryChannelE= nabled; - smc_pptable->DramBitWidth =3D smc_dpm_table->DramBitWidth; - smc_pptable->PaddingMem1[0] =3D smc_dpm_table->PaddingMem1[0]; - smc_pptable->PaddingMem1[1] =3D smc_dpm_table->PaddingMem1[1]; - smc_pptable->PaddingMem1[2] =3D smc_dpm_table->PaddingMem1[2]; - - /* Total board power */ - smc_pptable->TotalBoardPower =3D smc_dpm_table->TotalBoardPower; - smc_pptable->BoardPowerPadding =3D smc_dpm_table->BoardPowerPadding= ; - - /* XGMI Training */ - for (i =3D 0; i < NUM_XGMI_PSTATE_LEVELS; i++) { - smc_pptable->XgmiLinkSpeed[i] =3D smc_dpm_table->XgmiLinkSp= eed[i]; - smc_pptable->XgmiLinkWidth[i] =3D smc_dpm_table->XgmiLinkWi= dth[i]; - smc_pptable->XgmiFclkFreq[i] =3D smc_dpm_table->XgmiFclkFre= q[i]; - smc_pptable->XgmiSocVoltage[i] =3D smc_dpm_table->XgmiSocVo= ltage[i]; - } - + sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header)= ); + return 0; } -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D02%7C01%7Calexande= r.deucher%40amd.com%7Cbe47dcbc7575467cef3208d81808ddd3%7C3dd8961fe4884e608e= 11a82d994e183d%7C0%7C0%7C637285773673894951&sdata=3DgWPsTKZfNVQ1ug0x182= mDfLzsBLt%2FxK17kk69Rg6Hkw%3D&reserved=3D0 --_000_MN2PR12MB4488352EC87790ED63228C0BF7950MN2PR12MB4488namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Public Use]


Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
From: amd-gfx <amd-gfx-b= ounces@lists.freedesktop.org> on behalf of Likun Gao <likun.gao@amd.c= om>
Sent: Wednesday, June 24, 2020 2:35 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org&= gt;
Cc: Gao, Likun <Likun.Gao@amd.com>; Feng, Kenneth <Kenneth.= Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 1/2] drm/amd/powerplay: change method to set board p= arameters
 
From: Likun Gao <Likun.Gao@amd.com>

Copy board parameters directly instead of set each parameter for
sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
---
 .../drm/amd/powerplay/sienna_cichlid_ppt.c    | 89 = 3;------------------
 1 file changed, 2 insertions(+), 87 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/g= pu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 769e031d489a..693ad8963d0a 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -394,7 +394,6 @@ static int sienna_cichlid_append_powerplay_table(st= ruct smu_context *smu)
         PPTable_t *smc_pptable =3D= table_context->driver_pptable;
         struct atom_smc_dpm_info_v= 4_9 *smc_dpm_table;
         int index, ret;
-       int i;
 
         index =3D get_index_into_m= aster_table(atom_master_list_of_data_tables_v2_1,
            &nb= sp;            =             &nb= sp;       smc_dpm_info);
@@ -405,92 +404,8 @@ static int sienna_cichlid_append_powerplay_table(s= truct smu_context *smu)
            &nb= sp;    return ret;
 
         memcpy(smc_pptable->I2c= Controllers, smc_dpm_table->I2cControllers,
-            &n= bsp; sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
-
-       /* SVI2 Board Parameters */
-       smc_pptable->VddGfxVrMapping =3D s= mc_dpm_table->VddGfxVrMapping;
-       smc_pptable->VddSocVrMapping =3D s= mc_dpm_table->VddSocVrMapping;
-       smc_pptable->VddMem0VrMapping =3D = smc_dpm_table->VddMem0VrMapping;
-       smc_pptable->VddMem1VrMapping =3D = smc_dpm_table->VddMem1VrMapping;
-       smc_pptable->GfxUlvPhaseSheddingMa= sk =3D smc_dpm_table->GfxUlvPhaseSheddingMask;
-       smc_pptable->SocUlvPhaseSheddingMa= sk =3D smc_dpm_table->SocUlvPhaseSheddingMask;
-       smc_pptable->VddciUlvPhaseShedding= Mask =3D smc_dpm_table->VddciUlvPhaseSheddingMask;
-       smc_pptable->MvddUlvPhaseSheddingM= ask =3D smc_dpm_table->MvddUlvPhaseSheddingMask;
-
-       /* Telemetry Settings */
-       smc_pptable->GfxMaxCurrent =3D smc= _dpm_table->GfxMaxCurrent;
-       smc_pptable->GfxOffset =3D smc_dpm= _table->GfxOffset;
-       smc_pptable->Padding_TelemetryGfx = =3D smc_dpm_table->Padding_TelemetryGfx;
-       smc_pptable->SocMaxCurrent =3D smc= _dpm_table->SocMaxCurrent;
-       smc_pptable->SocOffset =3D smc_dpm= _table->SocOffset;
-       smc_pptable->Padding_TelemetrySoc = =3D smc_dpm_table->Padding_TelemetrySoc;
-       smc_pptable->Mem0MaxCurrent =3D sm= c_dpm_table->Mem0MaxCurrent;
-       smc_pptable->Mem0Offset =3D smc_dp= m_table->Mem0Offset;
-       smc_pptable->Padding_TelemetryMem0= =3D smc_dpm_table->Padding_TelemetryMem0;
-       smc_pptable->Mem1MaxCurrent =3D sm= c_dpm_table->Mem1MaxCurrent;
-       smc_pptable->Mem1Offset =3D smc_dp= m_table->Mem1Offset;
-       smc_pptable->Padding_TelemetryMem1= =3D smc_dpm_table->Padding_TelemetryMem1;
-       smc_pptable->MvddRatio =3D smc_dpm= _table->MvddRatio;
-
-       /* GPIO Settings */
-       smc_pptable->AcDcGpio =3D smc_dpm_= table->AcDcGpio;
-       smc_pptable->AcDcPolarity =3D smc_= dpm_table->AcDcPolarity;
-       smc_pptable->VR0HotGpio =3D smc_dp= m_table->VR0HotGpio;
-       smc_pptable->VR0HotPolarity =3D sm= c_dpm_table->VR0HotPolarity;
-       smc_pptable->VR1HotGpio =3D smc_dp= m_table->VR1HotGpio;
-       smc_pptable->VR1HotPolarity =3D sm= c_dpm_table->VR1HotPolarity;
-       smc_pptable->GthrGpio =3D smc_dpm_= table->GthrGpio;
-       smc_pptable->GthrPolarity =3D smc_= dpm_table->GthrPolarity;
-
-       /* LED Display Settings */
-       smc_pptable->LedPin0 =3D smc_dpm_t= able->LedPin0;
-       smc_pptable->LedPin1 =3D smc_dpm_t= able->LedPin1;
-       smc_pptable->LedPin2 =3D smc_dpm_t= able->LedPin2;
-       smc_pptable->LedEnableMask =3D smc= _dpm_table->LedEnableMask;
-       smc_pptable->LedPcie =3D smc_dpm_t= able->LedPcie;
-       smc_pptable->LedError =3D smc_dpm_= table->LedError;
-       smc_pptable->LedSpare1[0] =3D smc_= dpm_table->LedSpare1[0];
-       smc_pptable->LedSpare1[1] =3D smc_= dpm_table->LedSpare1[1];
-
-       /* GFXCLK PLL Spread Spectrum */
-       smc_pptable->PllGfxclkSpreadEnable= d =3D smc_dpm_table->PllGfxclkSpreadEnabled;
-       smc_pptable->PllGfxclkSpreadPercen= t =3D smc_dpm_table->PllGfxclkSpreadPercent;
-       smc_pptable->PllGfxclkSpreadFreq = =3D smc_dpm_table->PllGfxclkSpreadFreq;
-
-       /* GFXCLK DFLL Spread Spectrum */
-       smc_pptable->DfllGfxclkSpreadEnabl= ed =3D smc_dpm_table->DfllGfxclkSpreadEnabled;
-       smc_pptable->DfllGfxclkSpreadPerce= nt =3D smc_dpm_table->DfllGfxclkSpreadPercent;
-       smc_pptable->DfllGfxclkSpreadFreq = =3D smc_dpm_table->DfllGfxclkSpreadFreq;
-
-       /* UCLK Spread Spectrum */
-       smc_pptable->UclkSpreadEnabled =3D= smc_dpm_table->UclkSpreadEnabled;
-       smc_pptable->UclkSpreadPercent =3D= smc_dpm_table->UclkSpreadPercent;
-       smc_pptable->UclkSpreadFreq =3D sm= c_dpm_table->UclkSpreadFreq;
-
-       /* FCLK Spred Spectrum */
-       smc_pptable->FclkSpreadEnabled =3D= smc_dpm_table->FclkSpreadEnabled;
-       smc_pptable->FclkSpreadPercent =3D= smc_dpm_table->FclkSpreadPercent;
-       smc_pptable->FclkSpreadFreq =3D sm= c_dpm_table->FclkSpreadFreq;
-
-       /* Memory Config */
-       smc_pptable->MemoryChannelEnabled = =3D smc_dpm_table->MemoryChannelEnabled;
-       smc_pptable->DramBitWidth =3D smc_= dpm_table->DramBitWidth;
-       smc_pptable->PaddingMem1[0] =3D sm= c_dpm_table->PaddingMem1[0];
-       smc_pptable->PaddingMem1[1] =3D sm= c_dpm_table->PaddingMem1[1];
-       smc_pptable->PaddingMem1[2] =3D sm= c_dpm_table->PaddingMem1[2];
-
-       /* Total board power */
-       smc_pptable->TotalBoardPower =3D s= mc_dpm_table->TotalBoardPower;
-       smc_pptable->BoardPowerPadding =3D= smc_dpm_table->BoardPowerPadding;
-
-       /* XGMI Training */
-       for (i =3D 0; i < NUM_XGMI_PSTATE_= LEVELS; i++) {
-            &n= bsp;  smc_pptable->XgmiLinkSpeed[i] =3D smc_dpm_table->XgmiLinkS= peed[i];
-            &n= bsp;  smc_pptable->XgmiLinkWidth[i] =3D smc_dpm_table->XgmiLinkW= idth[i];
-            &n= bsp;  smc_pptable->XgmiFclkFreq[i] =3D smc_dpm_table->XgmiFclkFr= eq[i];
-            &n= bsp;  smc_pptable->XgmiSocVoltage[i] =3D smc_dpm_table->XgmiSocV= oltage[i];
-       }
-
+           &nbs= p;  sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));<= br> +      
         return 0;
 }
 
--
2.25.1

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