[AMD Public Use] While you are at it, can you clean up the local defines of these registers in drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c drivers/gpu/drm/amd/powerplay/smu_v12_0.c drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c and verify that the appropriate offset is used for both Renoir and raven? Alex ________________________________ From: amd-gfx on behalf of Tom St Denis Sent: Wednesday, March 25, 2020 3:22 PM To: amd-gfx@lists.freedesktop.org Cc: StDenis, Tom Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2) The PWR block was merged into the SMUIO block by revision 12 so we add that to the smuio_12_0_0 headers. (v2): Drop nonsensical smuio_10_0_0 header Signed-off-by: Tom St Denis --- .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++ .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h index 327b4d09f66d..9bf73284ad73 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h @@ -24,4 +24,7 @@ #define mmSMUIO_GFX_MISC_CNTL 0x00c8 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 +#define mmPWR_MISC_CNTL_STATUS 0x0183 +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1 + #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h index d815452cfd15..26556fa3d054 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h @@ -24,5 +24,10 @@ //SMUIO_GFX_MISC_CNTL #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 +//PWR_MISC_CNTL_STATUS +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L #endif -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Calexander.deucher%40amd.com%7C20b8d1812aac4516419c08d7d0f1de31%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637207609564642593&sdata=%2BT3BSejxB%2F3MsW8lfqAZ%2BiFfMXVG394Atnxi3K%2Bhjs8%3D&reserved=0