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boundary="===============0008088412==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0008088412== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB4488BD8607D8F25756B21DB0F7950MN2PR12MB4488namp_" --_000_MN2PR12MB4488BD8607D8F25756B21DB0F7950MN2PR12MB4488namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] Series is: Reviewed-by: Alex Deucher ________________________________ From: Jivin, Alex Sent: Wednesday, June 24, 2020 4:31 PM To: amd-gfx@lists.freedesktop.org Cc: Deucher, Alexander Subject: [PATCH 3/3] drm/amdgpu: SI support for UVD and VCE power managment Port functionality from the Radeon driver to support UVD and VCE power management. Signed-off-by: Alex Jivin --- drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 67 +++++++++++++++++++------- drivers/gpu/drm/amd/amdgpu/si_dpm.c | 19 ++++++++ 2 files changed, 68 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_pm.c index 347b06d3c140..26c8e39a78bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c @@ -3558,21 +3558,36 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *ad= ev, bool enable) { int ret =3D 0; - ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_U= VD, !enable); - if (ret) - DRM_ERROR("Dpm %s uvd failed, ret =3D %d. \n", - enable ? "enable" : "disable", ret); - - /* enable/disable Low Memory PState for UVD (4k videos) */ - if (adev->asic_type =3D=3D CHIP_STONEY && - adev->uvd.decode_image_width >=3D WIDTH_4K) { - struct pp_hwmgr *hwmgr =3D adev->powerplay.pp_handle; + if (adev->family =3D=3D AMDGPU_FAMILY_SI) { + if (enable) { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.uvd_active =3D true; + adev->pm.dpm.state =3D POWER_STATE_TYPE_INTERNAL_UV= D; + mutex_unlock(&adev->pm.mutex); + } else { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.uvd_active =3D false; + mutex_unlock(&adev->pm.mutex); + } - if (hwmgr && hwmgr->hwmgr_func && - hwmgr->hwmgr_func->update_nbdpm_pstate) - hwmgr->hwmgr_func->update_nbdpm_pstate(hwmgr, - !enable, - true); + amdgpu_pm_compute_clocks(adev); + } else { + ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOC= K_TYPE_UVD, !enable); + if (ret) + DRM_ERROR("Dpm %s uvd failed, ret =3D %d. \n", + enable ? "enable" : "disable", ret); + + /* enable/disable Low Memory PState for UVD (4k videos) */ + if (adev->asic_type =3D=3D CHIP_STONEY && + adev->uvd.decode_image_width >=3D WIDTH_4K) { + struct pp_hwmgr *hwmgr =3D adev->powerplay.pp_handl= e; + + if (hwmgr && hwmgr->hwmgr_func && + hwmgr->hwmgr_func->update_nbdpm_pstate) + hwmgr->hwmgr_func->update_nbdpm_pstate(hwmg= r, + !ena= ble, + true= ); + } } } @@ -3580,10 +3595,26 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *ad= ev, bool enable) { int ret =3D 0; - ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_V= CE, !enable); - if (ret) - DRM_ERROR("Dpm %s vce failed, ret =3D %d. \n", - enable ? "enable" : "disable", ret); + if (adev->family =3D=3D AMDGPU_FAMILY_SI) { + if (enable) { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active =3D true; + /* XXX select vce level based on ring/task */ + adev->pm.dpm.vce_level =3D AMD_VCE_LEVEL_AC_ALL; + mutex_unlock(&adev->pm.mutex); + } else { + mutex_lock(&adev->pm.mutex); + adev->pm.dpm.vce_active =3D false; + mutex_unlock(&adev->pm.mutex); + } + + amdgpu_pm_compute_clocks(adev); + } else { + ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOC= K_TYPE_VCE, !enable); + if (ret) + DRM_ERROR("Dpm %s vce failed, ret =3D %d. \n", + enable ? "enable" : "disable", ret); + } } void amdgpu_pm_print_power_states(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdg= pu/si_dpm.c index c00ba4b23c9a..ea914b256ebd 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c @@ -6953,6 +6953,24 @@ static int si_power_control_set_level(struct amdgpu_= device *adev) return 0; } +static void si_set_vce_clock(struct amdgpu_device *adev, + struct amdgpu_ps *new_rps, + struct amdgpu_ps *old_rps) +{ + if ((old_rps->evclk !=3D new_rps->evclk) || + (old_rps->ecclk !=3D new_rps->ecclk)) { + /* Turn the clocks on when encoding, off otherwise */ + if (new_rps->evclk || new_rps->ecclk) { + /* Place holder for future VCE1.0 porting to amdgpu + vce_v1_0_enable_mgcg(adev, false, false);*/ + } else { + /* Place holder for future VCE1.0 porting to amdgpu + vce_v1_0_enable_mgcg(adev, true, false); + amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, ne= w_rps->ecclk);*/ + } + } +} + static int si_dpm_set_power_state(void *handle) { struct amdgpu_device *adev =3D (struct amdgpu_device *)handle; @@ -7029,6 +7047,7 @@ static int si_dpm_set_power_state(void *handle) return ret; } ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps); + si_set_vce_clock(adev, new_ps, old_ps); if (eg_pi->pcie_performance_request) si_notify_link_speed_change_after_state_change(adev, new_p= s, old_ps); ret =3D si_set_power_state_conditionally_enable_ulv(adev, new_ps); -- 2.17.1 --_000_MN2PR12MB4488BD8607D8F25756B21DB0F7950MN2PR12MB4488namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Public Use]


Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
From: Jivin, Alex <Alex.= Jivin@amd.com>
Sent: Wednesday, June 24, 2020 4:31 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org&= gt;
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: SI support for UVD and VCE power ma= nagment
 
Port functionality from the Radeon driver to suppo= rt
UVD and VCE power management.

Signed-off-by: Alex Jivin <alex.jivin@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 67 +++++= ++++++++++++++-----= --
 drivers/gpu/drm/amd/amdgpu/si_dpm.c    | 19 ++= ++++++
 2 files changed, 68 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/a= mdgpu/amdgpu_pm.c
index 347b06d3c140..26c8e39a78bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -3558,21 +3558,36 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device= *adev, bool enable)
 {
         int ret =3D 0;
 
-       ret =3D amdgpu_dpm_set_powergating_by= _smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
-       if (ret)
-            &n= bsp;  DRM_ERROR("Dpm %s uvd failed, ret =3D %d. \n",
-            &n= bsp;            enab= le ? "enable" : "disable", ret);
-
-       /* enable/disable Low Memory PState f= or UVD (4k videos) */
-       if (adev->asic_type =3D=3D CHIP_ST= ONEY &&
-            &n= bsp;  adev->uvd.decode_image_width >=3D WIDTH_4K) {
-            &n= bsp;  struct pp_hwmgr *hwmgr =3D adev->powerplay.pp_handle;
+       if (adev->family =3D=3D AMDGPU= _FAMILY_SI) {
+           &nbs= p;   if (enable) {
+           &nbs= p;           mutex_lock(&= amp;adev->pm.mutex);
+           &nbs= p;           adev->pm.= dpm.uvd_active =3D true;
+           &nbs= p;           adev->pm.= dpm.state =3D POWER_STATE_TYPE_INTERNAL_UVD;
+           &nbs= p;           mutex_unlock= (&adev->pm.mutex);
+           &nbs= p;   } else {
+           &nbs= p;           mutex_lock(&= amp;adev->pm.mutex);
+           &nbs= p;           adev->pm.= dpm.uvd_active =3D false;
+           &nbs= p;           mutex_unlock= (&adev->pm.mutex);
+           &nbs= p;   }
 
-            &n= bsp;  if (hwmgr && hwmgr->hwmgr_func &&
-            &n= bsp;      hwmgr->hwmgr_func->update_nbdpm_ps= tate)
-            &n= bsp;          hwmgr->hwmgr_= func->update_nbdpm_pstate(hwmgr,
-            &n= bsp;            = ;            &n= bsp;            = ;            !enable= ,
-            &n= bsp;            = ;            &n= bsp;            = ;            true);<= br> +           &nbs= p;   amdgpu_pm_compute_clocks(adev);
+       } else {
+           &nbs= p;   ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK= _TYPE_UVD, !enable);
+           &nbs= p;   if (ret)
+           &nbs= p;           DRM_ERROR(&q= uot;Dpm %s uvd failed, ret =3D %d. \n",
+           &nbs= p;            &= nbsp;        enable ? "enable"= : "disable", ret);
+
+           &nbs= p;   /* enable/disable Low Memory PState for UVD (4k videos) */ +           &nbs= p;   if (adev->asic_type =3D=3D CHIP_STONEY &&
+           &nbs= p;           adev->uvd= .decode_image_width >=3D WIDTH_4K) {
+           &nbs= p;           struct pp_hw= mgr *hwmgr =3D adev->powerplay.pp_handle;
+
+           &nbs= p;           if (hwmgr &a= mp;& hwmgr->hwmgr_func &&
+           &nbs= p;            &= nbsp;  hwmgr->hwmgr_func->update_nbdpm_pstate)
+           &nbs= p;            &= nbsp;      hwmgr->hwmgr_func->update_nbdpm_p= state(hwmgr,
+           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;        !enable,
+           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;        true);
+           &nbs= p;   }
         }
 }
 
@@ -3580,10 +3595,26 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device= *adev, bool enable)
 {
         int ret =3D 0;
 
-       ret =3D amdgpu_dpm_set_powergating_by= _smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
-       if (ret)
-            &n= bsp;  DRM_ERROR("Dpm %s vce failed, ret =3D %d. \n",
-            &n= bsp;            enab= le ? "enable" : "disable", ret);
+       if (adev->family =3D=3D AMDGPU= _FAMILY_SI) {
+           &nbs= p;   if (enable) {
+           &nbs= p;           mutex_lock(&= amp;adev->pm.mutex);
+           &nbs= p;           adev->pm.= dpm.vce_active =3D true;
+           &nbs= p;           /* XXX selec= t vce level based on ring/task */
+           &nbs= p;           adev->pm.= dpm.vce_level =3D AMD_VCE_LEVEL_AC_ALL;
+           &nbs= p;           mutex_unlock= (&adev->pm.mutex);
+           &nbs= p;   } else {
+           &nbs= p;           mutex_lock(&= amp;adev->pm.mutex);
+           &nbs= p;           adev->pm.= dpm.vce_active =3D false;
+           &nbs= p;           mutex_unlock= (&adev->pm.mutex);
+           &nbs= p;   }
+
+           &nbs= p;   amdgpu_pm_compute_clocks(adev);
+       } else {
+           &nbs= p;   ret =3D amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK= _TYPE_VCE, !enable);
+           &nbs= p;   if (ret)
+           &nbs= p;           DRM_ERROR(&q= uot;Dpm %s vce failed, ret =3D %d. \n",
+           &nbs= p;            &= nbsp;        enable ? "enable"= : "disable", ret);
+       }
 }
 
 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dpm.c b/drivers/gpu/drm/amd/amdg= pu/si_dpm.c
index c00ba4b23c9a..ea914b256ebd 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dpm.c
@@ -6953,6 +6953,24 @@ static int si_power_control_set_level(struct amd= gpu_device *adev)
         return 0;
 }
 
+static void si_set_vce_clock(struct amdgpu_device *adev,
+           &nbs= p;            &= nbsp;   struct amdgpu_ps *new_rps,
+           &nbs= p;            &= nbsp;   struct amdgpu_ps *old_rps)
+{
+       if ((old_rps->evclk !=3D new_r= ps->evclk) ||
+           (old_rps-= >ecclk !=3D new_rps->ecclk)) {
+           &nbs= p;   /* Turn the clocks on when encoding, off otherwise */
+           &nbs= p;   if (new_rps->evclk || new_rps->ecclk) {
+           &nbs= p;           /* Place hol= der for future VCE1.0 porting to amdgpu
+           &nbs= p;           vce_v1_0_ena= ble_mgcg(adev, false, false);*/
+           &nbs= p;   } else {
+           &nbs= p;           /* Place hol= der for future VCE1.0 porting to amdgpu
+           &nbs= p;           vce_v1_0_ena= ble_mgcg(adev, true, false);
+           &nbs= p;           amdgpu_asic_= set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/
+           &nbs= p;   }
+       }
+}
+
 static int si_dpm_set_power_state(void *handle)
 {
         struct amdgpu_device *adev= =3D (struct amdgpu_device *)handle;
@@ -7029,6 +7047,7 @@ static int si_dpm_set_power_state(void *handle)             &nb= sp;    return ret;
         }
         ni_set_uvd_clock_after_set= _eng_clock(adev, new_ps, old_ps);
+       si_set_vce_clock(adev, new_ps, ol= d_ps);
         if (eg_pi->pcie_perform= ance_request)
            &nb= sp;    si_notify_link_speed_change_after_state_change(adev, = new_ps, old_ps);
         ret =3D si_set_power_state= _conditionally_enable_ulv(adev, new_ps);
--
2.17.1

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