* [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
@ 2020-10-26 16:14 Alex Deucher
2020-10-27 15:20 ` Alex Deucher
0 siblings, 1 reply; 3+ messages in thread
From: Alex Deucher @ 2020-10-26 16:14 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher
This is required for MALL. Was accidently removed in PRS update.
Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is enabled")
Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
index f3ae208850b0..cc2eca8c9a62 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
@@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
break;
}
+ if (dc->current_state->stream_count == 1 // single display only
+ && dc->current_state->stream_status[0].plane_count == 1 // single surface only
+ && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
+ // Only 8 and 16 bit formats
+ && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
+ && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
+ surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
+ dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
+ (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
+ 8 : 4);
+ } else {
+ // TODO: remove hard code size
+ surface_size = 128 * 1024 * 1024;
+ }
+
// TODO: remove hard code size
if (surface_size < 128 * 1024 * 1024) {
refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
--
2.25.4
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
2020-10-26 16:14 [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c Alex Deucher
@ 2020-10-27 15:20 ` Alex Deucher
2020-10-27 15:27 ` Abramov, Slava
0 siblings, 1 reply; 3+ messages in thread
From: Alex Deucher @ 2020-10-27 15:20 UTC (permalink / raw)
To: amd-gfx list; +Cc: Alex Deucher
Ping?
On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> This is required for MALL. Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
> break;
> }
>
> + if (dc->current_state->stream_count == 1 // single display only
> + && dc->current_state->stream_status[0].plane_count == 1 // single surface only
> + && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
> + // Only 8 and 16 bit formats
> + && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> + && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
> + surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
> + dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
> + (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> + 8 : 4);
> + } else {
> + // TODO: remove hard code size
> + surface_size = 128 * 1024 * 1024;
> + }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
2020-10-27 15:20 ` Alex Deucher
@ 2020-10-27 15:27 ` Abramov, Slava
0 siblings, 0 replies; 3+ messages in thread
From: Abramov, Slava @ 2020-10-27 15:27 UTC (permalink / raw)
To: Alex Deucher, amd-gfx list; +Cc: Deucher, Alexander
[-- Attachment #1.1: Type: text/plain, Size: 3610 bytes --]
[AMD Official Use Only - Internal Distribution Only]
Looks sane to me.
Acked-by: Slava Abramov <slava.abramov@amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Alex Deucher <alexdeucher@gmail.com>
Sent: Tuesday, October 27, 2020 11:20 AM
To: amd-gfx list <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH] drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.c
Ping?
On Mon, Oct 26, 2020 at 12:14 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> This is required for MALL. Was accidently removed in PRS update.
>
> Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is enabled")
> Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)")
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> index f3ae208850b0..cc2eca8c9a62 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
> @@ -715,6 +715,21 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
> break;
> }
>
> + if (dc->current_state->stream_count == 1 // single display only
> + && dc->current_state->stream_status[0].plane_count == 1 // single surface only
> + && dc->current_state->stream_status[0].plane_states[0]->address.page_table_base.quad_part == 0 // no VM
> + // Only 8 and 16 bit formats
> + && dc->current_state->stream_status[0].plane_states[0]->format <= SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F
> + && dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB8888) {
> + surface_size = dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_pitch *
> + dc->current_state->stream_status[0].plane_states[0]->plane_size.surface_size.height *
> + (dc->current_state->stream_status[0].plane_states[0]->format >= SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ?
> + 8 : 4);
> + } else {
> + // TODO: remove hard code size
> + surface_size = 128 * 1024 * 1024;
> + }
> +
> // TODO: remove hard code size
> if (surface_size < 128 * 1024 * 1024) {
> refresh_hz = div_u64((unsigned long long) dc->current_state->streams[0]->timing.pix_clk_100hz *
> --
> 2.25.4
>
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2020-10-27 15:20 ` Alex Deucher
2020-10-27 15:27 ` Abramov, Slava
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