From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2265A3D7E for ; Tue, 16 Aug 2022 14:06:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CA9B7C433D7; Tue, 16 Aug 2022 14:06:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660658809; bh=Or6NyDZrBzLzCXiIiquybOJRFR8o21mNOuu9wwm7Nss=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kfw1O86y2BXK91mGj0emsKUZkIdWk32UmBAWTwQjudeEvHAasXBTJndVb1TuUneDD rVYTtbvFMo+QhYNl2UJK1HMfxu4hKojAVWqZgsyNUoFb+rzPxq+zFxDKs66QJCCtm1 2txEOXrlVzP3vE7EMu24gEtSP6dRv/3DcWqeW7duIlMCeqnVBXuK8jgabfBzlCc7/l fZUv+oaFllnBBMxHS/Q+r5R49NpjKKAEXV5lQOrXfgAPGq2AdzcdlZM1kUydwTcJBV JTanTDke6p8gRxBvtYYFcMNyInC9y26AtCwzencBxBL6osJm5XT9OcY9JsudLnfkc7 XbYfPc765w6cA== Date: Tue, 16 Aug 2022 15:06:41 +0100 From: Will Deacon To: Arnd Bergmann Cc: Hector Martin , Peter Zijlstra , Ingo Molnar , Alan Stern , Andrea Parri , Boqun Feng , Nicholas Piggin , David Howells , Jade Alglave , Luc Maranget , "Paul E. McKenney" , Akira Yokosawa , Daniel Lustig , Joel Fernandes , Mark Rutland , Jonathan Corbet , Tejun Heo , jirislaby@kernel.org, Marc Zyngier , Catalin Marinas , Oliver Neukum , Linus Torvalds , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Asahi Linux , stable@vger.kernel.org Subject: Re: [PATCH] locking/atomic: Make test_and_*_bit() ordered on failure Message-ID: <20220816140640.GD11202@willie-the-truck> References: <20220816070311.89186-1-marcan@marcan.st> Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) On Tue, Aug 16, 2022 at 10:16:04AM +0200, Arnd Bergmann wrote: > On Tue, Aug 16, 2022 at 9:03 AM Hector Martin wrote: > > > > These operations are documented as always ordered in > > include/asm-generic/bitops/instrumented-atomic.h, and producer-consumer > > type use cases where one side needs to ensure a flag is left pending > > after some shared data was updated rely on this ordering, even in the > > failure case. > > > > This is the case with the workqueue code, which currently suffers from a > > reproducible ordering violation on Apple M1 platforms (which are > > notoriously out-of-order) that ends up causing the TTY layer to fail to > > deliver data to userspace properly under the right conditions. This > > change fixes that bug. > > > > Change the documentation to restrict the "no order on failure" story to > > the _lock() variant (for which it makes sense), and remove the > > early-exit from the generic implementation, which is what causes the > > missing barrier semantics in that case. Without this, the remaining > > atomic op is fully ordered (including on ARM64 LSE, as of recent > > versions of the architecture spec). > > > > Suggested-by: Linus Torvalds > > Cc: stable@vger.kernel.org > > Fixes: e986a0d6cb36 ("locking/atomics, asm-generic/bitops/atomic.h: Rewrite using atomic_*() APIs") > > Fixes: 61e02392d3c7 ("locking/atomic/bitops: Document and clarify ordering semantics for failed test_and_{}_bit()") > > Signed-off-by: Hector Martin > > --- > > Documentation/atomic_bitops.txt | 2 +- > > include/asm-generic/bitops/atomic.h | 6 ------ > > I double-checked all the architecture specific implementations to ensure > that the asm-generic one is the only one that needs the fix. I couldn't figure out parisc -- do you know what ordering their spinlocks provide? They have a comment talking about a release, but I don't know what the ordering guarantees of an "ldcw" are. Will