From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from casper.infradead.org (casper.infradead.org [90.155.50.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F7796AA7 for ; Tue, 16 Aug 2022 18:14:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=MySzvGXqRSaBBJhmsw3ulDhggVAysoOKEMJnaszkKsU=; b=YPrEDcLvKjIb0xNBG+Jk/CGOJ6 kW006eJ0NtmQgEuIfrtpv18W/AT3E6P4tU5tApVpU7iXAmUuqgW37qBLQwW2Knu5FTIuqME+NNPyp YadFUKbPi+Tq8trcm0xs6iZy0i2DBc3igLK50MYONBYKHxtUkGtlV31WJyX2fPAFh1cO7W3lL6vBo rNXj8n/uobl/HADOp+sc3StKPN9OlbxVN+x6YSldP1qDn+vr9g7EePepooP8GXvGf41FpHgOg9w5Q eUbNbWIvPg7EMgqcJ9XQFTfQntotK8qMPpjXTNgqVHkWILVngJ8OwCDNX5OV/DmArUSafNpj+lANo lPG7MazQ==; Received: from willy by casper.infradead.org with local (Exim 4.94.2 #2 (Red Hat Linux)) id 1oO153-007DVO-MT; Tue, 16 Aug 2022 18:14:21 +0000 Date: Tue, 16 Aug 2022 19:14:21 +0100 From: Matthew Wilcox To: Will Deacon Cc: Arnd Bergmann , Hector Martin , Peter Zijlstra , Ingo Molnar , Alan Stern , Andrea Parri , Boqun Feng , Nicholas Piggin , David Howells , Jade Alglave , Luc Maranget , "Paul E. McKenney" , Akira Yokosawa , Daniel Lustig , Joel Fernandes , Mark Rutland , Jonathan Corbet , Tejun Heo , jirislaby@kernel.org, Marc Zyngier , Catalin Marinas , Oliver Neukum , Linus Torvalds , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Asahi Linux , stable@vger.kernel.org Subject: Re: [PATCH] locking/atomic: Make test_and_*_bit() ordered on failure Message-ID: References: <20220816070311.89186-1-marcan@marcan.st> <20220816140640.GD11202@willie-the-truck> Precedence: bulk X-Mailing-List: asahi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220816140640.GD11202@willie-the-truck> On Tue, Aug 16, 2022 at 03:06:41PM +0100, Will Deacon wrote: > On Tue, Aug 16, 2022 at 10:16:04AM +0200, Arnd Bergmann wrote: > > On Tue, Aug 16, 2022 at 9:03 AM Hector Martin wrote: > > > > > > These operations are documented as always ordered in > > > include/asm-generic/bitops/instrumented-atomic.h, and producer-consumer > > > type use cases where one side needs to ensure a flag is left pending > > > after some shared data was updated rely on this ordering, even in the > > > failure case. > > > > > > This is the case with the workqueue code, which currently suffers from a > > > reproducible ordering violation on Apple M1 platforms (which are > > > notoriously out-of-order) that ends up causing the TTY layer to fail to > > > deliver data to userspace properly under the right conditions. This > > > change fixes that bug. > > > > > > Change the documentation to restrict the "no order on failure" story to > > > the _lock() variant (for which it makes sense), and remove the > > > early-exit from the generic implementation, which is what causes the > > > missing barrier semantics in that case. Without this, the remaining > > > atomic op is fully ordered (including on ARM64 LSE, as of recent > > > versions of the architecture spec). > > > > > > Suggested-by: Linus Torvalds > > > Cc: stable@vger.kernel.org > > > Fixes: e986a0d6cb36 ("locking/atomics, asm-generic/bitops/atomic.h: Rewrite using atomic_*() APIs") > > > Fixes: 61e02392d3c7 ("locking/atomic/bitops: Document and clarify ordering semantics for failed test_and_{}_bit()") > > > Signed-off-by: Hector Martin > > > --- > > > Documentation/atomic_bitops.txt | 2 +- > > > include/asm-generic/bitops/atomic.h | 6 ------ > > > > I double-checked all the architecture specific implementations to ensure > > that the asm-generic one is the only one that needs the fix. > > I couldn't figure out parisc -- do you know what ordering their spinlocks > provide? They have a comment talking about a release, but I don't know what > the ordering guarantees of an "ldcw" are. "The semaphore operation is strongly ordered" (that's from the description of the LDCW instruction)