From mboxrd@z Thu Jan  1 00:00:00 1970
From: Adrian Chadd <adrian@freebsd.org>
Date: Thu, 25 Aug 2016 08:48:07 -0700
Subject: [ath9k-devel] Interrupt issue on ARM with SMP
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Does the ARM board do legacy interrupts as well as MSI?


-a


On 24 August 2016 at 20:50, Lamar Hansford <Lamar.Hansford@maxpoint.com> wrote:
> Hi,
> I am trying to port the driver to an ARM platform using SMP where we see a hard lock-up (no panic).  To address this and a number of secondary issues I am refactoring the interrupt handling code and I need to understand the interrupt hand-shake process.
>
> I am using:
> *  NVidia T30
> * AR9485 (AR9003)
>
> My current understanding of  the code is:
> -1-  ISR
>     -1- disable all interrupts (IER|AR_INTR_ASYNC_ENABLE|AR_INTR_SYNC_ENABLE)
>     -2- schedule tasklet
> -2- Tasklet (enable interrupts)
>     -1- write default AR_IER
>     -2- write default AR_INTR_ASYNC_ENABLE
>     -3- write default AR_INTR_ASYNC_MASK
>     -4- write default AR_INTR_SYNC_ENABLE
>     -5- write default AR_INTR_SYNC_MASK
>
> I would like to change this to:
> -1-  ISR
>     -1- mask interrupt to be handled
> -2- Tasklet (unmask interrupts)
>     -1- Un-mask interrupts which are handled
>
> TEST SCENARIO:
> * Set interface to manual in /etc/networking/interfaces
> * modprobe ath9k
> * iw wlan0 set monitor none
> * ifconfig wlan0 up
>
> ISSUES:
> * I see only two interrupts after reset_complete
> * in the first interrupt ATH_OP_HW_RESET is pending.  So ignored
> * The second interrupt occurs very close in time after reset_complete which follows sequence below
> * no more interrupts
>
> ath_isr
> [ 3551.293766] ath: phy6: ISR-IRQ-ISR: 0x81000012
> [ 3551.298242] ath: phy6: ISR-IRQ-IMR: 0x81800175
> [ 3551.302718] ath: phy6: ISR-IRQ-IMR2: 0xc10000
>
> ar9003_hw_get_isr
> [ 3385.525838] ath: phy6: ATH9K REG-ISR-ASYNC-CAUSE: 0 (0x0)
> [ 3385.531271] ath: phy6: ATH9K REG-ISR-ASYNC-MASK: 2 (0x2)
> [ 3385.536617] ath: phy6: ATH9K REG-ISR-SYNC-CAUSE: 0 (0x0)
> [ 3385.541961] ath: phy6: ATH9K REG-ISR-SYNC-MASK: 23f60
> [ 3385.547133] ath: phy6: ATH9K REG-ISR-ISR: 0x0, (0x81000012)
>
> Causing the ISR  not being processed due to:
>         if (!isr && !sync_cause && !async_cause)
>                 return false;
> and
>         if (async_cause & async_mask) {
>                 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
>                                 == AR_RTC_STATUS_ON){
>                         isr = REG_READ(ah, AR_ISR);
>                 }
>         }
>
> If I ignore these and read/process the ISR anyway I still get no further interrupts. I only get sleep timer  calls.
>
> On x86 (which works) I get coninual interrupts which exhibit the following:
> Aug 25 03:15:09 s0000 kernel: [190154.647784] ath: phy52: AR_IMR 0x81800175 IER 0x1
> Aug 25 03:15:09 s0000 kernel: [190154.651795] ath: phy52: ATH9K-ISR IMR: 0x81800175
> Aug 25 03:15:09 s0000 kernel: [190154.651804] ath: phy52: ATH9K-ISR IMR2: 0xc10000
> Aug 25 03:15:09 s0000 kernel: [190154.651810] ath: phy52: ATH9K-ISR ISR: 0x4
> Aug 25 03:15:09 s0000 kernel: [190154.651820] ath: phy52: ATH9K REG-ISR-ASYNC-CAUSE: 2
> Aug 25 03:15:09 s0000 kernel: [190154.651824] ath: phy52: ATH9K REG-ISR-ASYNC-MASK: 2
> Aug 25 03:15:09 s0000 kernel: [190154.651827] ath: phy52: ATH9K REG-ISR-SYNC: 0
>
> Any ideas what to explore next?
>
> Additional questions:
> * What is the process to mask interrupts?
> * Is it possible to mask interrupts without disabling all of them? (normally interrupts remain enabled but only the procedure is masked until serviced).
>
>
>
>
>
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