From mboxrd@z Thu Jan 1 00:00:00 1970 From: Adrian Chadd Date: Sat, 27 Aug 2016 21:44:39 -0700 Subject: [ath9k-devel] Interrupt issue on ARM with SMP In-Reply-To: References: Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: ath9k-devel@lists.ath9k.org Hi, So, interrupt handling is finnicky. It's possible there's already a posted interrupt waiting somewhere. Ideally you'd do a write-then-read in each of the interrupt blocks between your device and the CPU to ensure thing are synced. Otherwise the different frequencies in different blocks in the ARM code mean you get interrupts after you've cleared the interrupt itself, because it hasn't yet posted in that particular hardware block. Yay, etc. -adrian