Re: [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups

From: "Cédric Le Goater" <clg@kaod.org>
To: Richard Henderson <richard.henderson@linaro.org>,
	<qemu-devel@nongnu.org>
Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, alex.bennee@linaro.org
Subject: Re: [RFC PATCH for-7.0 00/35] target/ppc fpu fixes and cleanups
Date: Fri, 3 Dec 2021 11:36:22 +0100	[thread overview]
Message-ID: <b85f3c68-7643-be41-9c7b-6475932725d6@kaod.org> (raw)
In-Reply-To: <20211119160502.17432-1-richard.henderson@linaro.org>

On 11/19/21 17:04, Richard Henderson wrote:
> This is a partial patch set showing the direction I believe
> the cleanups should go, as opposed to a complete conversion.
> 
> I add a bunch of float_flag_* bits that diagnose the reason
> for most float_flag_invalid, as guided by the requirements
> of the PowerPC VX* bits.  I have converted some helpers to
> use these new flags but not all.  A good signal for unconverted
> routines is the use of float*_is_signalling_nan, which should
> now be using float_flag_invalid_snan.
> 
> I added float64x32_* arithmetic routines, which take float64
> arguments and round the result to the range and precision of
> float32, while giving the result in float64 form.  This is
> exactly what PowerPC requires for its single-precision math.
> This fixes double-rounding problems that exist in the current
> code, and are visible in the float_madds test.
> 
> I add test reference files for float_madds and float_convs
> after fixing the bugs required to make the tests pass.
> 
> 
> r~
> 
> 
> Richard Henderson (35):
>    softfloat: Extend float_exception_flags to 16 bits
>    softfloat: Add flag specific to Inf - Inf
>    softfloat: Add flag specific to Inf * 0
>    softfloat: Add flags specific to Inf / Inf and 0 / 0
>    softfloat: Add flag specific to sqrt(-x)
>    softfloat: Add flag specific to convert non-nan to int
>    softfloat: Add flag specific to signaling nans
>    target/ppc: Update float_invalid_op_addsub for new flags
>    target/ppc: Update float_invalid_op_mul for new flags
>    target/ppc: Update float_invalid_op_div for new flags
>    target/ppc: Move float_check_status from FPU_FCTI to translate
>    target/ppc: Update float_invalid_cvt for new flags
>    target/ppc: Fix VXCVI return value
>    target/ppc: Remove inline from do_fri
>    target/ppc: Use FloatRoundMode in do_fri
>    target/ppc: Tidy inexact handling in do_fri
>    target/ppc: Clean up do_fri
>    target/ppc: Update fmadd for new flags
>    target/ppc: Split out do_fmadd
>    target/ppc: Do not call do_float_check_status from do_fmadd
>    target/ppc: Split out do_frsp
>    target/ppc: Update do_frsp for new flags
>    target/ppc: Use helper_todouble in do_frsp
>    target/ppc: Update sqrt for new flags
>    target/ppc: Update xsrqpi and xsrqpxp to new flags
>    target/ppc: Update fre to new flags
>    softfloat: Add float64r32 arithmetic routines
>    target/ppc: Add helpers for fmadds et al
>    target/ppc: Add helper for fsqrts
>    target/ppc: Add helpers for fadds, fsubs, fdivs
>    target/ppc: Add helper for fmuls
>    target/ppc: Add helper for frsqrtes
>    target/ppc: Update fres to new flags and float64r32
>    target/ppc: Use helper_todouble/tosingle in helper_xststdcsp
>    test/tcg/ppc64le: Add float reference files

I didn't see any regression, so I plan to queue the first 34 patches
for 7.0 and let you handle the last patch since there is a small fix
to address before.

Thanks,

C.