From: Chris Wilson <chris@chris-wilson.co.uk>
To: Jesse Barnes <jbarnes@virtuousgeek.org>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall
Date: Tue, 23 Oct 2012 12:42:07 +0100 [thread overview]
Message-ID: <b94cdc$725i4v@fmsmga001.fm.intel.com> (raw)
In-Reply-To: <1350583639-773-7-git-send-email-jbarnes@virtuousgeek.org>
On Thu, 18 Oct 2012 13:07:18 -0500, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> "If ENABLED, PIPE_CONTROL command will flush the in flight data written
> out by render engine to Global Observation point on flush done. Also
> Requires stall bit ([20] of DW1) set."
That quotation doesn't make sense in the context of TLB invalidation,
and the programming guide here very carefully avoids the mention of
requiring any stall bit set for the post-sync op of TLB invalidation.
Maybe quote chapter and verse as well?
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
next prev parent reply other threads:[~2012-10-23 12:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-18 18:07 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 2/8] drm/i915: implement WaDisableDopClockGatingisable on VLV and IVB Jesse Barnes
2012-10-18 18:07 ` [PATCH 3/8] drm/i915: implement WaForceL3Serialization " Jesse Barnes
2012-10-18 18:07 ` [PATCH 4/8] drm/i915: implement WaDisableVLVClockGating_VBIIssue on VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 5/8] drm/i915: implement WaDisablePSDDualDispatchEnable on IVB & VLV Jesse Barnes
2012-10-18 18:07 ` [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_SW requires a post-sync op Jesse Barnes
2012-10-23 11:22 ` Chris Wilson
2012-10-23 14:28 ` Jesse Barnes
2012-10-18 18:07 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-23 11:42 ` Chris Wilson [this message]
2012-10-25 18:28 ` Jesse Barnes
2012-10-18 18:07 ` [PATCH 8/8] drm/i915: add clock gating regs to VLV offset check function Jesse Barnes
-- strict thread matches above, loose matches on Subject: below --
2012-10-25 19:15 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-25 19:15 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
2012-10-18 15:43 [PATCH 1/8] drm/i915: implement WaDisableL3CacheAging on VLV Jesse Barnes
2012-10-18 15:43 ` [PATCH 7/8] drm/i915: PIPE_CONTROL TLB invalidate requires CS stall Jesse Barnes
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