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Marchesi) To: Jiong Wang Cc: binutils@sourceware.org, Alexei Starovoitov , Daniel Borkmann , bpf@vger.kernel.org Subject: Re: [PATCH 0/9] eBPF support for GNU binutils References: <1B2BE52B-527E-436E-AE49-29FA9E044FD3@netronome.com> Date: Tue, 21 May 2019 19:06:21 +0200 In-Reply-To: <1B2BE52B-527E-436E-AE49-29FA9E044FD3@netronome.com> (Jiong Wang's message of "Tue, 21 May 2019 16:41:56 +0100") Message-ID: <87d0kbrb3m.fsf@oracle.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9264 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 suspectscore=0 malwarescore=0 phishscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=870 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905210104 X-Proofpoint-Virus-Version: vendor=nai engine=5900 definitions=9264 signatures=668687 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=961 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1905210105 Sender: bpf-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: bpf@vger.kernel.org Hi Jiong. > Despite using a different syntax for the assembler (the llvm assembler > uses a C-ish expression-based syntax while the GNU assembler opts for > a more classic assembly-language syntax) this implementation tries to > provide inter-operability with clang/llvm generated objects. =20=20=20=20 I also noticed your implementation doesn=E2=80=99t seem to use the same= sub-register syntax as what LLVM assembler is doing. =20=20=20=20 x register for 64-bit, and w register for 32-bit sub-register. =20=20=20=20 So: add r0, r1, r2 means BPF_ALU64 | BPF_ADD | BFF_X add w0, w1, w1 means BPF_ALU | BPF_ADD | BPF_X =20=20=20=20 ASAICT, different register prefix for different register width is also = adopted by quite a few other GNU assembler targets like AArch64, X86_64. Right. I opted for using different mnemonics for alu and alu64 instructions, as it seemed to be simpler. What was your rationale for using sub-register notation? Are you planning to support instructions (or pseudo-instructions) mixing w and x registers in the future? > In particular, the numbers of the relocations used for instruction > fields are the same. These are R_BPF_INSN_64 and R_BPF_INSN_DISP32. > The later is resolved at load-time by bpf_load.c. =20=20=20=20 I think you missed the latest JMP32 instructions. =20=20=20=20 https://github.com/torvalds/linux/blob/master/Documentation/networkin= g/filter.txt#L870 Oh thanks for spotting that. Adding support for it :)