From: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>
To: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v6 02/64] drm/i915: Pin timeline map after first timeline pin, v3.
Date: Mon, 18 Jan 2021 11:28:48 +0100 [thread overview]
Message-ID: <c482a326-8885-8027-4485-80dbefc23e13@shipmail.org> (raw)
In-Reply-To: <20210105153558.134272-3-maarten.lankhorst@linux.intel.com>
Reviewed-by: Thomas Hellström <thomas.hellstrom@intel.com>
On 1/5/21 4:34 PM, Maarten Lankhorst wrote:
> We're starting to require the reservation lock for pinning,
> so wait until we have that.
>
> Update the selftests to handle this correctly, and ensure pin is
> called in live_hwsp_rollover_user() and mock_hwsp_freelist().
>
> Changes since v1:
> - Fix NULL + XX arithmatic, use casts. (kbuild)
> Changes since v2:
> - Clear entire cacheline when pinning.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> Reported-by: kernel test robot <lkp@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_timeline.c | 40 +++++++++----
> drivers/gpu/drm/i915/gt/intel_timeline.h | 2 +
> drivers/gpu/drm/i915/gt/mock_engine.c | 22 ++++++-
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 63 +++++++++++----------
> drivers/gpu/drm/i915/i915_selftest.h | 2 +
> 5 files changed, 84 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index 3d43f15f34f3..7509af471341 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -53,14 +53,29 @@ static int __timeline_active(struct i915_active *active)
> return 0;
> }
>
> +I915_SELFTEST_EXPORT int
> +intel_timeline_pin_map(struct intel_timeline *timeline)
> +{
> + struct drm_i915_gem_object *obj = timeline->hwsp_ggtt->obj;
> + u32 ofs = offset_in_page(timeline->hwsp_offset);
> + void *vaddr;
> +
> + vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
> + if (IS_ERR(vaddr))
> + return PTR_ERR(vaddr);
> +
> + timeline->hwsp_map = vaddr;
> + timeline->hwsp_seqno = memset(vaddr + ofs, 0, CACHELINE_BYTES);
> + clflush(vaddr + ofs);
> +
> + return 0;
> +}
> +
> static int intel_timeline_init(struct intel_timeline *timeline,
> struct intel_gt *gt,
> struct i915_vma *hwsp,
> unsigned int offset)
> {
> - void *vaddr;
> - u32 *seqno;
> -
> kref_init(&timeline->kref);
> atomic_set(&timeline->pin_count, 0);
>
> @@ -77,14 +92,8 @@ static int intel_timeline_init(struct intel_timeline *timeline,
> timeline->hwsp_ggtt = hwsp;
> }
>
> - vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
> - if (IS_ERR(vaddr))
> - return PTR_ERR(vaddr);
> -
> - timeline->hwsp_map = vaddr;
> - seqno = vaddr + timeline->hwsp_offset;
> - WRITE_ONCE(*seqno, 0);
> - timeline->hwsp_seqno = seqno;
> + timeline->hwsp_map = NULL;
> + timeline->hwsp_seqno = (void *)(long)timeline->hwsp_offset;
>
> GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
>
> @@ -114,7 +123,8 @@ static void intel_timeline_fini(struct rcu_head *rcu)
> struct intel_timeline *timeline =
> container_of(rcu, struct intel_timeline, rcu);
>
> - i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
> + if (timeline->hwsp_map)
> + i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
>
> i915_vma_put(timeline->hwsp_ggtt);
> i915_active_fini(&timeline->active);
> @@ -174,6 +184,12 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
> if (atomic_add_unless(&tl->pin_count, 1, 0))
> return 0;
>
> + if (!tl->hwsp_map) {
> + err = intel_timeline_pin_map(tl);
> + if (err)
> + return err;
> + }
> +
> err = i915_ggtt_pin(tl->hwsp_ggtt, ww, 0, PIN_HIGH);
> if (err)
> return err;
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.h b/drivers/gpu/drm/i915/gt/intel_timeline.h
> index f502a619843f..c50543d3ed5d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.h
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.h
> @@ -110,4 +110,6 @@ void intel_gt_show_timelines(struct intel_gt *gt,
> const char *prefix,
> int indent));
>
> +I915_SELFTEST_DECLARE(int intel_timeline_pin_map(struct intel_timeline *tl));
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c b/drivers/gpu/drm/i915/gt/mock_engine.c
> index 2f830017c51d..effbac877eec 100644
> --- a/drivers/gpu/drm/i915/gt/mock_engine.c
> +++ b/drivers/gpu/drm/i915/gt/mock_engine.c
> @@ -32,9 +32,20 @@
> #include "mock_engine.h"
> #include "selftests/mock_request.h"
>
> -static void mock_timeline_pin(struct intel_timeline *tl)
> +static int mock_timeline_pin(struct intel_timeline *tl)
> {
> + int err;
> +
> + if (WARN_ON(!i915_gem_object_trylock(tl->hwsp_ggtt->obj)))
> + return -EBUSY;
> +
> + err = intel_timeline_pin_map(tl);
> + i915_gem_object_unlock(tl->hwsp_ggtt->obj);
> + if (err)
> + return err;
> +
> atomic_inc(&tl->pin_count);
> + return 0;
> }
>
> static void mock_timeline_unpin(struct intel_timeline *tl)
> @@ -152,6 +163,8 @@ static void mock_context_destroy(struct kref *ref)
>
> static int mock_context_alloc(struct intel_context *ce)
> {
> + int err;
> +
> ce->ring = mock_ring(ce->engine);
> if (!ce->ring)
> return -ENOMEM;
> @@ -162,7 +175,12 @@ static int mock_context_alloc(struct intel_context *ce)
> return PTR_ERR(ce->timeline);
> }
>
> - mock_timeline_pin(ce->timeline);
> + err = mock_timeline_pin(ce->timeline);
> + if (err) {
> + intel_timeline_put(ce->timeline);
> + ce->timeline = NULL;
> + return err;
> + }
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 6e32e91cdab4..2e2bea7ac7a5 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -35,7 +35,7 @@ static unsigned long hwsp_cacheline(struct intel_timeline *tl)
> {
> unsigned long address = (unsigned long)page_address(hwsp_page(tl));
>
> - return (address + tl->hwsp_offset) / CACHELINE_BYTES;
> + return (address + offset_in_page(tl->hwsp_offset)) / CACHELINE_BYTES;
> }
>
> #define CACHELINES_PER_PAGE (PAGE_SIZE / CACHELINE_BYTES)
> @@ -59,6 +59,7 @@ static void __mock_hwsp_record(struct mock_hwsp_freelist *state,
> tl = xchg(&state->history[idx], tl);
> if (tl) {
> radix_tree_delete(&state->cachelines, hwsp_cacheline(tl));
> + intel_timeline_unpin(tl);
> intel_timeline_put(tl);
> }
> }
> @@ -78,6 +79,12 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
> if (IS_ERR(tl))
> return PTR_ERR(tl);
>
> + err = intel_timeline_pin(tl, NULL);
> + if (err) {
> + intel_timeline_put(tl);
> + return err;
> + }
> +
> cacheline = hwsp_cacheline(tl);
> err = radix_tree_insert(&state->cachelines, cacheline, tl);
> if (err) {
> @@ -85,6 +92,7 @@ static int __mock_hwsp_timeline(struct mock_hwsp_freelist *state,
> pr_err("HWSP cacheline %lu already used; duplicate allocation!\n",
> cacheline);
> }
> + intel_timeline_unpin(tl);
> intel_timeline_put(tl);
> return err;
> }
> @@ -452,7 +460,7 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> }
>
> static struct i915_request *
> -tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
> +checked_tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
> {
> struct i915_request *rq;
> int err;
> @@ -463,6 +471,13 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
> goto out;
> }
>
> + if (READ_ONCE(*tl->hwsp_seqno) != tl->seqno) {
> + pr_err("Timeline created with incorrect breadcrumb, found %x, expected %x\n",
> + *tl->hwsp_seqno, tl->seqno);
> + intel_timeline_unpin(tl);
> + return ERR_PTR(-EINVAL);
> + }
> +
> rq = intel_engine_create_kernel_request(engine);
> if (IS_ERR(rq))
> goto out_unpin;
> @@ -484,25 +499,6 @@ tl_write(struct intel_timeline *tl, struct intel_engine_cs *engine, u32 value)
> return rq;
> }
>
> -static struct intel_timeline *
> -checked_intel_timeline_create(struct intel_gt *gt)
> -{
> - struct intel_timeline *tl;
> -
> - tl = intel_timeline_create(gt);
> - if (IS_ERR(tl))
> - return tl;
> -
> - if (READ_ONCE(*tl->hwsp_seqno) != tl->seqno) {
> - pr_err("Timeline created with incorrect breadcrumb, found %x, expected %x\n",
> - *tl->hwsp_seqno, tl->seqno);
> - intel_timeline_put(tl);
> - return ERR_PTR(-EINVAL);
> - }
> -
> - return tl;
> -}
> -
> static int live_hwsp_engine(void *arg)
> {
> #define NUM_TIMELINES 4096
> @@ -535,13 +531,13 @@ static int live_hwsp_engine(void *arg)
> struct intel_timeline *tl;
> struct i915_request *rq;
>
> - tl = checked_intel_timeline_create(gt);
> + tl = intel_timeline_create(gt);
> if (IS_ERR(tl)) {
> err = PTR_ERR(tl);
> break;
> }
>
> - rq = tl_write(tl, engine, count);
> + rq = checked_tl_write(tl, engine, count);
> if (IS_ERR(rq)) {
> intel_timeline_put(tl);
> err = PTR_ERR(rq);
> @@ -608,14 +604,14 @@ static int live_hwsp_alternate(void *arg)
> if (!intel_engine_can_store_dword(engine))
> continue;
>
> - tl = checked_intel_timeline_create(gt);
> + tl = intel_timeline_create(gt);
> if (IS_ERR(tl)) {
> err = PTR_ERR(tl);
> goto out;
> }
>
> intel_engine_pm_get(engine);
> - rq = tl_write(tl, engine, count);
> + rq = checked_tl_write(tl, engine, count);
> intel_engine_pm_put(engine);
> if (IS_ERR(rq)) {
> intel_timeline_put(tl);
> @@ -1258,6 +1254,10 @@ static int live_hwsp_rollover_user(void *arg)
> if (!tl->has_initial_breadcrumb)
> goto out;
>
> + err = intel_context_pin(ce);
> + if (err)
> + goto out;
> +
> tl->seqno = -4u;
> WRITE_ONCE(*(u32 *)tl->hwsp_seqno, tl->seqno);
>
> @@ -1267,7 +1267,7 @@ static int live_hwsp_rollover_user(void *arg)
> this = intel_context_create_request(ce);
> if (IS_ERR(this)) {
> err = PTR_ERR(this);
> - goto out;
> + goto out_unpin;
> }
>
> pr_debug("%s: create fence.seqnp:%d\n",
> @@ -1286,17 +1286,18 @@ static int live_hwsp_rollover_user(void *arg)
> if (i915_request_wait(rq[2], 0, HZ / 5) < 0) {
> pr_err("Wait for timeline wrap timed out!\n");
> err = -EIO;
> - goto out;
> + goto out_unpin;
> }
>
> for (i = 0; i < ARRAY_SIZE(rq); i++) {
> if (!i915_request_completed(rq[i])) {
> pr_err("Pre-wrap request not completed!\n");
> err = -EINVAL;
> - goto out;
> + goto out_unpin;
> }
> }
> -
> +out_unpin:
> + intel_context_unpin(ce);
> out:
> for (i = 0; i < ARRAY_SIZE(rq); i++)
> i915_request_put(rq[i]);
> @@ -1338,13 +1339,13 @@ static int live_hwsp_recycle(void *arg)
> struct intel_timeline *tl;
> struct i915_request *rq;
>
> - tl = checked_intel_timeline_create(gt);
> + tl = intel_timeline_create(gt);
> if (IS_ERR(tl)) {
> err = PTR_ERR(tl);
> break;
> }
>
> - rq = tl_write(tl, engine, count);
> + rq = checked_tl_write(tl, engine, count);
> if (IS_ERR(rq)) {
> intel_timeline_put(tl);
> err = PTR_ERR(rq);
> diff --git a/drivers/gpu/drm/i915/i915_selftest.h b/drivers/gpu/drm/i915/i915_selftest.h
> index d53d207ab6eb..f54de0499be7 100644
> --- a/drivers/gpu/drm/i915/i915_selftest.h
> +++ b/drivers/gpu/drm/i915/i915_selftest.h
> @@ -107,6 +107,7 @@ int __i915_subtests(const char *caller,
>
> #define I915_SELFTEST_DECLARE(x) x
> #define I915_SELFTEST_ONLY(x) unlikely(x)
> +#define I915_SELFTEST_EXPORT
>
> #else /* !IS_ENABLED(CONFIG_DRM_I915_SELFTEST) */
>
> @@ -116,6 +117,7 @@ static inline int i915_perf_selftests(struct pci_dev *pdev) { return 0; }
>
> #define I915_SELFTEST_DECLARE(x)
> #define I915_SELFTEST_ONLY(x) 0
> +#define I915_SELFTEST_EXPORT static
>
> #endif
>
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next prev parent reply other threads:[~2021-01-18 10:36 UTC|newest]
Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-05 15:34 [Intel-gfx] [PATCH v6 00/64] drm/i915: Remove obj->mm.lock! Maarten Lankhorst
2021-01-05 15:34 ` [Intel-gfx] [PATCH v6 01/64] drm/i915: Do not share hwsp across contexts any more, v6 Maarten Lankhorst
2021-01-14 12:06 ` Tvrtko Ursulin
2021-01-18 16:09 ` Maarten Lankhorst
2021-01-05 15:34 ` [Intel-gfx] [PATCH v6 02/64] drm/i915: Pin timeline map after first timeline pin, v3 Maarten Lankhorst
2021-01-18 10:28 ` Thomas Hellström (Intel) [this message]
2021-01-05 15:34 ` [Intel-gfx] [PATCH v6 03/64] drm/i915: Move cmd parser pinning to execbuffer Maarten Lankhorst
2021-01-05 15:34 ` [Intel-gfx] [PATCH v6 04/64] drm/i915: Add missing -EDEADLK handling to execbuf pinning, v2 Maarten Lankhorst
2021-01-05 15:34 ` [Intel-gfx] [PATCH v6 05/64] drm/i915: Ensure we hold the object mutex in pin correctly Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 06/64] drm/i915: Add gem object locking to madvise Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 07/64] drm/i915: Move HAS_STRUCT_PAGE to obj->flags Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 08/64] drm/i915: Rework struct phys attachment handling Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 09/64] drm/i915: Convert i915_gem_object_attach_phys() to ww locking, v2 Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 10/64] drm/i915: make lockdep slightly happier about execbuf Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 11/64] drm/i915: Disable userptr pread/pwrite support Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 12/64] drm/i915: No longer allow exporting userptr through dma-buf Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 13/64] drm/i915: Reject more ioctls for userptr Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 14/64] drm/i915: Reject UNSYNCHRONIZED for userptr, v2 Maarten Lankhorst
2021-01-11 20:50 ` Dave Airlie
2021-01-18 10:34 ` Thomas Hellström
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 15/64] drm/i915: Make compilation of userptr code depend on MMU_NOTIFIER Maarten Lankhorst
2021-01-18 11:17 ` Thomas Hellström
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 16/64] drm/i915: Fix userptr so we do not have to worry about obj->mm.lock, v5 Maarten Lankhorst
2021-01-11 20:51 ` Dave Airlie
2021-01-18 11:30 ` Thomas Hellström (Intel)
2021-01-18 12:43 ` Maarten Lankhorst
2021-01-18 12:55 ` Thomas Hellström (Intel)
2021-01-18 14:43 ` Maarten Lankhorst
2021-01-20 13:32 ` Thomas Hellström (Intel)
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 17/64] drm/i915: Flatten obj->mm.lock Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 18/64] drm/i915: Populate logical context during first pin Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 19/64] drm/i915: Make ring submission compatible with obj->mm.lock removal, v2 Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 20/64] drm/i915: Handle ww locking in init_status_page Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 21/64] drm/i915: Rework clflush to work correctly without obj->mm.lock Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 22/64] drm/i915: Pass ww ctx to intel_pin_to_display_plane Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 23/64] drm/i915: Add object locking to vm_fault_cpu Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 24/64] drm/i915: Move pinning to inside engine_wa_list_verify() Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 25/64] drm/i915: Take reservation lock around i915_vma_pin Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 26/64] drm/i915: Make lrc_init_wa_ctx compatible with ww locking Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 27/64] drm/i915: Make __engine_unpark() " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 28/64] drm/i915: Take obj lock around set_domain ioctl Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 29/64] drm/i915: Defer pin calls in buffer pool until first use by caller Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 30/64] drm/i915: Fix pread/pwrite to work with new locking rules Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 31/64] drm/i915: Fix workarounds selftest, part 1 Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 32/64] drm/i915: Prepare for obj->mm.lock removal Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 33/64] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 34/64] drm/i915: Add ww locking around vm_access() Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 35/64] drm/i915: Increase ww locking for perf Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 36/64] drm/i915: Lock ww in ucode objects correctly Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 37/64] drm/i915: Add ww locking to dma-buf ops Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 38/64] drm/i915: Add missing ww lock in intel_dsb_prepare Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 39/64] drm/i915: Fix ww locking in shmem_create_from_object Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 40/64] drm/i915: Use a single page table lock for each gtt Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 41/64] drm/i915/selftests: Prepare huge_pages testcases for obj->mm.lock removal Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 42/64] drm/i915/selftests: Prepare client blit " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 43/64] drm/i915/selftests: Prepare coherency tests " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 44/64] drm/i915/selftests: Prepare context " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 45/64] drm/i915/selftests: Prepare dma-buf " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 46/64] drm/i915/selftests: Prepare execbuf " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 47/64] drm/i915/selftests: Prepare mman testcases " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 48/64] drm/i915/selftests: Prepare object tests " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 49/64] drm/i915/selftests: Prepare object blit " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 50/64] drm/i915/selftests: Prepare igt_gem_utils " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 51/64] drm/i915/selftests: Prepare context selftest " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 52/64] drm/i915/selftests: Prepare hangcheck " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 53/64] drm/i915/selftests: Prepare execlists and lrc selftests " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 54/64] drm/i915/selftests: Prepare mocs tests " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 55/64] drm/i915/selftests: Prepare ring submission " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 56/64] drm/i915/selftests: Prepare timeline tests " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 57/64] drm/i915/selftests: Prepare i915_request " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 58/64] drm/i915/selftests: Prepare memory region " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 59/64] drm/i915/selftests: Prepare cs engine " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 60/64] drm/i915/selftests: Prepare gtt " Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 61/64] drm/i915: Finally remove obj->mm.lock Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 62/64] drm/i915: Keep userpointer bindings if seqcount is unchanged, v2 Maarten Lankhorst
2021-01-18 10:58 ` Thomas Hellström
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 63/64] drm/i915: Move gt_revoke() slightly Maarten Lankhorst
2021-01-18 11:11 ` Thomas Hellström
2021-01-18 12:01 ` Maarten Lankhorst
2021-01-18 13:22 ` Thomas Hellström
2021-01-18 13:28 ` Thomas Hellström
2021-01-18 14:46 ` Maarten Lankhorst
2021-01-18 15:05 ` Thomas Hellström
2021-01-18 15:32 ` Maarten Lankhorst
2021-01-05 15:35 ` [Intel-gfx] [PATCH v6 64/64] drm/i915: Avoid some false positives in assert_object_held() Maarten Lankhorst
2021-01-05 17:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove obj->mm.lock! (rev12) Patchwork
2021-01-05 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-05 17:29 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-01-07 15:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Remove obj->mm.lock! (rev13) Patchwork
2021-01-07 15:44 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-01-07 15:47 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-01-07 16:11 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
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