From mboxrd@z Thu Jan 1 00:00:00 1970 From: prabhakar.mahadev-lad.rj@bp.renesas.com (Lad Prabhakar) Date: Wed, 5 Feb 2020 20:38:29 +0000 Subject: [cip-dev] [PATCH 4.19.y-cip 03/35] arm64: dts: renesas: r8a774b1: Add CAN and CAN FD support In-Reply-To: <1580935141-1173-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <1580935141-1173-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> Message-ID: <1580935141-1173-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com> To: cip-dev@lists.cip-project.org List-Id: cip-dev.lists.cip-project.org From: Fabrizio Castro commit 3fa08cbb0662acc6cbd1a481956570a52dba8875 upstream. Add CAN and CAN FD support to the RZ/G2N SoC specific dtsi. Signed-off-by: Fabrizio Castro Link: https://lore.kernel.org/r/1570717560-7431-4-git-send-email-fabrizio.castro at bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Lad Prabhakar --- arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 48 +++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index 65d39ae..a8ed475 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -849,18 +849,60 @@ }; can0: can at e6c30000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c30000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; }; can1: can at e6c38000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; reg = <0 0xe6c38000 0 0x1000>; - /* placeholder */ + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; }; canfd: can at e66c0000 { + compatible = "renesas,r8a774b1-canfd", + "renesas,rcar-gen3-canfd"; reg = <0 0xe66c0000 0 0x8000>; - /* placeholder */ + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; }; scif0: serial at e6e60000 { -- 2.7.4