From: Lad Prabhakar commit 31941342888d4fa008fb27cef9d4ae5913df8792 upstream. Add SDHI[0-2] device nodes to R8A774E1 SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1594811350-14066-11-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven Signed-off-by: Biju Das --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 32 ++++++++++++++++++++--- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 12e11bed3da8..838f8f0440cf 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1269,17 +1269,42 @@ }; sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + iommus = <&ipmmu_ds1 32>; status = "disabled"; + }; - /* placeholder */ + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + iommus = <&ipmmu_ds1 33>; + status = "disabled"; }; sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + iommus = <&ipmmu_ds1 34>; status = "disabled"; - - /* placeholder */ }; sdhi3: mmc@ee160000 { @@ -1291,6 +1316,7 @@ max-frequency = <200000000>; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 311>; + iommus = <&ipmmu_ds1 35>; status = "disabled"; }; -- 2.17.1