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* [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
@ 2020-10-12 14:18 Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features Lad Prabhakar
                   ` (51 more replies)
  0 siblings, 52 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 5957 bytes --]

Hi All,

This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
RZ/G2x platforms.

* Required EP framework changes and fixes are ported as well.
* All the patches have been cheery picked from upstream kernel.
* Patches [43, 44, 45, 46, 48]/50 are picked from linux-next.
* I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
  this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
  for suggestions if this can be handled differently.
* In patch 37/48 I have dropped the changes for host driver as the patch
  doesn't apply cleanly and manually applying it was resulting in a big diff.
* As the changes touches three other controller drivers I have build tested them
  as done similarly while upstreaming R-Car Gen3 PCIe EP driver.
* Since the changes are huge I am sending the patches as RFC.

Cheers,
Prabhakar

Alan Mikhak (5):
  PCI: endpoint: Set endpoint controller pointer to NULL
  PCI: endpoint: Allocate enough space for fixed size BAR
  PCI: endpoint: Skip odd BAR when skipping 64bit BAR
  PCI: endpoint: Clear BAR before freeing its space
  PCI: endpoint: Cast the page number to phys_addr_t

Hewenliang (1):
  tools: PCI: Fix fd leakage

Jean-Jacques Hiblot (1):
  tools: PCI: Exit with error code when test fails

Kangjie Lu (1):
  PCI: endpoint: Fix a potential NULL pointer dereference

Kishon Vijay Abraham I (23):
  PCI: endpoint: Add new pci_epc_ops to get EPC features
  PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
  PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
  PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
  PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
  PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
  PCI: endpoint: Add helper to get first unreserved BAR
  PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
  PCI: pci-epf-test: Remove setting epf_bar flags in function driver
  PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is
    64Bit
  PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
  PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
  PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
  PCI: designware-plat: Remove setting epc->features in Designware plat
    EP driver
  PCI: endpoint: Remove features member in struct pci_epc
  PCI: endpoint: Add support to specify alignment for buffers allocated
    to BARs
  PCI: endpoint: Use notification chain mechanism to notify EPC events
    to EPF
  PCI: endpoint: Replace spinlock with mutex
  PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
  PCI: endpoint: Assign function number for each PF in EPC core
  PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
  PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table
    address
  PCI: endpoint: functions/pci-epf-test: Print throughput information

Kunihiko Hayashi (1):
  PCI: endpoint: Fix clearing start entry in configfs

Lad Prabhakar (15):
  PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
  PCI: endpoint: Add support to handle multiple base for mapping
    outbound memory
  PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
  arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
  PCI: rcar: Move shareable code to a common file
  PCI: rcar: Fix calculating mask for PCIEPAMR register
  dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint
    controller
  PCI: rcar: Add endpoint mode support
  arm64: defconfig: Enable R-Car PCIe endpoint driver
  dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
  arm64: dts: renesas: r8a774c0: Add PCIe EP node
  arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
  arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
  misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller
  misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe
    controllers

Vidya Sagar (3):
  PCI: endpoint: Add core init notifying feature
  PCI: endpoint: Add notification for core init completion
  PCI: pci-epf-test: Add support to defer core initialization

 .../devicetree/bindings/pci/rcar-pci-ep.yaml  |   80 ++
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi     |   38 +
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi     |   38 +
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi     |   19 +
 arch/arm64/configs/defconfig                  |    7 +-
 drivers/misc/pci_endpoint_test.c              |    7 +
 drivers/pci/controller/Kconfig                |   18 +
 drivers/pci/controller/Makefile               |    3 +-
 drivers/pci/controller/dwc/pci-dra7xx.c       |   13 +
 .../pci/controller/dwc/pcie-designware-ep.c   |   39 +-
 .../pci/controller/dwc/pcie-designware-plat.c |   17 +-
 drivers/pci/controller/dwc/pcie-designware.h  |    1 +
 drivers/pci/controller/pcie-cadence-ep.c      |   27 +-
 drivers/pci/controller/pcie-rcar-ep.c         |  563 ++++++++
 drivers/pci/controller/pcie-rcar-host.c       | 1264 +++++++++++++++++
 drivers/pci/controller/pcie-rcar.c            | 1224 +---------------
 drivers/pci/controller/pcie-rcar.h            |  140 ++
 drivers/pci/controller/pcie-rockchip-ep.c     |   18 +-
 drivers/pci/endpoint/functions/pci-epf-test.c |  295 +++-
 drivers/pci/endpoint/pci-ep-cfs.c             |   28 +-
 drivers/pci/endpoint/pci-epc-core.c           |  187 ++-
 drivers/pci/endpoint/pci-epc-mem.c            |  204 ++-
 drivers/pci/endpoint/pci-epf-core.c           |   49 +-
 include/linux/pci-epc.h                       |   95 +-
 include/linux/pci-epf.h                       |   32 +-
 tools/pci/pcitest.c                           |    5 +-
 26 files changed, 2919 insertions(+), 1492 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
 create mode 100644 drivers/pci/controller/pcie-rcar-ep.c
 create mode 100644 drivers/pci/controller/pcie-rcar-host.c
 create mode 100644 drivers/pci/controller/pcie-rcar.h

-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 02/50] PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops Lad Prabhakar
                   ` (50 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 3941 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 41cb8d189c9d4964df52a6f497cab7b301ae831b upstream.

Add a new pci_epc_ops ->get_features() to get the features
supported by the EPC. Since EPC can provide different features to
different functions, the ->get_features() ops takes _func_no_ as
an argument.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-core.c | 30 +++++++++++++++++++++++++++++
 include/linux/pci-epc.h             | 22 +++++++++++++++++++++
 2 files changed, 52 insertions(+)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 094dcc3203b8..5a099479d9ab 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -83,6 +83,36 @@ struct pci_epc *pci_epc_get(const char *epc_name)
 }
 EXPORT_SYMBOL_GPL(pci_epc_get);
 
+/**
+ * pci_epc_get_features() - get the features supported by EPC
+ * @epc: the features supported by *this* EPC device will be returned
+ * @func_no: the features supported by the EPC device specific to the
+ *	     endpoint function with func_no will be returned
+ *
+ * Invoke to get the features provided by the EPC which may be
+ * specific to an endpoint function. Returns pci_epc_features on success
+ * and NULL for any failures.
+ */
+const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
+						    u8 func_no)
+{
+	const struct pci_epc_features *epc_features;
+	unsigned long flags;
+
+	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
+		return NULL;
+
+	if (!epc->ops->get_features)
+		return NULL;
+
+	spin_lock_irqsave(&epc->lock, flags);
+	epc_features = epc->ops->get_features(epc, func_no);
+	spin_unlock_irqrestore(&epc->lock, flags);
+
+	return epc_features;
+}
+EXPORT_SYMBOL_GPL(pci_epc_get_features);
+
 /**
  * pci_epc_stop() - stop the PCI link
  * @epc: the link of the EPC device that has to be stopped
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 931fda3e5e0d..fcd5e5047546 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -59,6 +59,8 @@ struct pci_epc_ops {
 			     enum pci_epc_irq_type type, u16 interrupt_num);
 	int	(*start)(struct pci_epc *epc);
 	void	(*stop)(struct pci_epc *epc);
+	const struct pci_epc_features* (*get_features)(struct pci_epc *epc,
+						       u8 func_no);
 	struct module *owner;
 };
 
@@ -103,6 +105,24 @@ struct pci_epc {
 	unsigned int			features;
 };
 
+/**
+ * struct pci_epc_features - features supported by a EPC device per function
+ * @linkup_notifier: indicate if the EPC device can notify EPF driver on link up
+ * @msi_capable: indicate if the endpoint function has MSI capability
+ * @msix_capable: indicate if the endpoint function has MSI-X capability
+ * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
+ * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
+ * @bar_fixed_size: Array specifying the size supported by each BAR
+ */
+struct pci_epc_features {
+	unsigned int	linkup_notifier : 1;
+	unsigned int	msi_capable : 1;
+	unsigned int	msix_capable : 1;
+	u8	reserved_bar;
+	u8	bar_fixed_64bit;
+	u64	bar_fixed_size[BAR_5 + 1];
+};
+
 #define EPC_FEATURE_NO_LINKUP_NOTIFIER		BIT(0)
 #define EPC_FEATURE_BAR_MASK			(BIT(1) | BIT(2) | BIT(3))
 #define EPC_FEATURE_MSIX_AVAILABLE		BIT(4)
@@ -161,6 +181,8 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
 		      enum pci_epc_irq_type type, u16 interrupt_num);
 int pci_epc_start(struct pci_epc *epc);
 void pci_epc_stop(struct pci_epc *epc);
+const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
+						    u8 func_no);
 struct pci_epc *pci_epc_get(const char *epc_name);
 void pci_epc_put(struct pci_epc *epc);
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 02/50] PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 03/50] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Lad Prabhakar
                   ` (49 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2354 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit fee35cb76a54c87985410ea6aa12002e5d38b367 upstream.

Each platform using Designware PCIe core can support different set of
endpoint features. Add a new callback function ->get_features() in
dw_pcie_ep_ops so that each platform using Designware PCIe core can
advertise its supported features to the endpoint function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/dwc/pcie-designware-ep.c | 12 ++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h    |  1 +
 2 files changed, 13 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index a3d07d9c598b..d1bb4b852b6c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -355,6 +355,17 @@ static int dw_pcie_ep_start(struct pci_epc *epc)
 	return pci->ops->start_link(pci);
 }
 
+static const struct pci_epc_features*
+dw_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+
+	if (!ep->ops->get_features)
+		return NULL;
+
+	return ep->ops->get_features(ep);
+}
+
 static const struct pci_epc_ops epc_ops = {
 	.write_header		= dw_pcie_ep_write_header,
 	.set_bar		= dw_pcie_ep_set_bar,
@@ -368,6 +379,7 @@ static const struct pci_epc_ops epc_ops = {
 	.raise_irq		= dw_pcie_ep_raise_irq,
 	.start			= dw_pcie_ep_start,
 	.stop			= dw_pcie_ep_stop,
+	.get_features		= dw_pcie_ep_get_features,
 };
 
 int dw_pcie_ep_raise_legacy_irq(struct dw_pcie_ep *ep, u8 func_no)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 14dcf6646699..90f978f2d1b0 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -181,6 +181,7 @@ struct dw_pcie_ep_ops {
 	void	(*ep_init)(struct dw_pcie_ep *ep);
 	int	(*raise_irq)(struct dw_pcie_ep *ep, u8 func_no,
 			     enum pci_epc_irq_type type, u16 interrupt_num);
+	const struct pci_epc_features* (*get_features)(struct dw_pcie_ep *ep);
 };
 
 struct dw_pcie_ep {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 03/50] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 02/50] PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 04/50] PCI: pci-dra7xx: " Lad Prabhakar
                   ` (48 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1494 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 3b4322e589a630fe35944ced5852655fcc4a5d24 upstream.

Populate ->get_features() dw_pcie_ep_ops to return the EPC features
supported by Designware PCIe endpoint controller.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/dwc/pcie-designware-plat.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index c12bf794d69c..bd0516afc86f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -100,9 +100,22 @@ static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+static const struct pci_epc_features dw_plat_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = true,
+};
+
+static const struct pci_epc_features*
+dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
+{
+	return &dw_plat_pcie_epc_features;
+}
+
 static struct dw_pcie_ep_ops pcie_ep_ops = {
 	.ep_init = dw_plat_pcie_ep_init,
 	.raise_irq = dw_plat_pcie_ep_raise_irq,
+	.get_features = dw_plat_pcie_get_features,
 };
 
 static int dw_plat_add_pcie_port(struct dw_plat_pcie *dw_plat_pcie,
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 04/50] PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (2 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 03/50] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 05/50] PCI: rockchip: " Lad Prabhakar
                   ` (47 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1424 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 4894467e78619232a79e39c2f26ae8378c4500ed upstream.

Populate ->get_features() dw_pcie_ep_ops to return the EPC features
supported by DRA7xx PCIe endpoint controller.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/dwc/pci-dra7xx.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index 412524aa1fde..49417092f5e3 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -390,9 +390,22 @@ static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	return 0;
 }
 
+static const struct pci_epc_features dra7xx_pcie_epc_features = {
+	.linkup_notifier = true,
+	.msi_capable = true,
+	.msix_capable = false,
+};
+
+static const struct pci_epc_features*
+dra7xx_pcie_get_features(struct dw_pcie_ep *ep)
+{
+	return &dra7xx_pcie_epc_features;
+}
+
 static struct dw_pcie_ep_ops pcie_ep_ops = {
 	.ep_init = dra7xx_pcie_ep_init,
 	.raise_irq = dra7xx_pcie_raise_irq,
+	.get_features = dra7xx_pcie_get_features,
 };
 
 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 05/50] PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (3 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 04/50] PCI: pci-dra7xx: " Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 06/50] PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops Lad Prabhakar
                   ` (46 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1677 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 146221768c74bbd969f968b61ec95a0254a6b311 upstream.

Populate ->get_features() dw_pcie_ep_ops to return the EPC features
supported by Rockchip PCIe endpoint controller.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-rockchip-ep.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index caf34661d38d..ab6478334101 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -505,6 +505,18 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc)
 	return 0;
 }
 
+static const struct pci_epc_features rockchip_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = false,
+};
+
+static const struct pci_epc_features*
+rockchip_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+	return &rockchip_pcie_epc_features;
+}
+
 static const struct pci_epc_ops rockchip_pcie_epc_ops = {
 	.write_header	= rockchip_pcie_ep_write_header,
 	.set_bar	= rockchip_pcie_ep_set_bar,
@@ -515,6 +527,7 @@ static const struct pci_epc_ops rockchip_pcie_epc_ops = {
 	.get_msi	= rockchip_pcie_ep_get_msi,
 	.raise_irq	= rockchip_pcie_ep_raise_irq,
 	.start		= rockchip_pcie_ep_start,
+	.get_features	= rockchip_pcie_ep_get_features,
 };
 
 static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 06/50] PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (4 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 05/50] PCI: rockchip: " Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 07/50] PCI: endpoint: Add helper to get first unreserved BAR Lad Prabhakar
                   ` (45 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1615 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 67c777e6015d857a5e9662c68281d83d946d9b70 upstream.

Populate ->get_features() dw_pcie_ep_ops to return the EPC features
supported by Cadence PCIe endpoint controller.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-cadence-ep.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index c3a088910f48..14c2545bb17e 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -411,6 +411,18 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
 	return 0;
 }
 
+static const struct pci_epc_features cdns_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = false,
+};
+
+static const struct pci_epc_features*
+cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+	return &cdns_pcie_epc_features;
+}
+
 static const struct pci_epc_ops cdns_pcie_epc_ops = {
 	.write_header	= cdns_pcie_ep_write_header,
 	.set_bar	= cdns_pcie_ep_set_bar,
@@ -421,6 +433,7 @@ static const struct pci_epc_ops cdns_pcie_epc_ops = {
 	.get_msi	= cdns_pcie_ep_get_msi,
 	.raise_irq	= cdns_pcie_ep_raise_irq,
 	.start		= cdns_pcie_ep_start,
+	.get_features	= cdns_pcie_ep_get_features,
 };
 
 static const struct of_device_id cdns_pcie_ep_of_match[] = {
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 07/50] PCI: endpoint: Add helper to get first unreserved BAR
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (5 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 06/50] PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 08/50] PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags Lad Prabhakar
                   ` (44 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2250 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 1e9efe6c9976552e88c6e6feaca3a78b8cf5aaf6 upstream.

Add a helper function pci_epc_get_first_free_bar() to get the first
unreserved BAR that can be used for endpoint function.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-core.c | 23 +++++++++++++++++++++++
 include/linux/pci-epc.h             |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 5a099479d9ab..e4712a0f249c 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -83,6 +83,29 @@ struct pci_epc *pci_epc_get(const char *epc_name)
 }
 EXPORT_SYMBOL_GPL(pci_epc_get);
 
+/**
+ * pci_epc_get_first_free_bar() - helper to get first unreserved BAR
+ * @epc_features: pci_epc_features structure that holds the reserved bar bitmap
+ *
+ * Invoke to get the first unreserved BAR that can be used for endpoint
+ * function. For any incorrect value in reserved_bar return '0'.
+ */
+unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
+					*epc_features)
+{
+	int free_bar;
+
+	if (!epc_features)
+		return 0;
+
+	free_bar = ffz(epc_features->reserved_bar);
+	if (free_bar > 5)
+		return 0;
+
+	return free_bar;
+}
+EXPORT_SYMBOL_GPL(pci_epc_get_first_free_bar);
+
 /**
  * pci_epc_get_features() - get the features supported by EPC
  * @epc: the features supported by *this* EPC device will be returned
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index fcd5e5047546..dcaecf715b1c 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -183,6 +183,8 @@ int pci_epc_start(struct pci_epc *epc);
 void pci_epc_stop(struct pci_epc *epc);
 const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
 						    u8 func_no);
+unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
+					*epc_features);
 struct pci_epc *pci_epc_get(const char *epc_name);
 void pci_epc_put(struct pci_epc *epc);
 
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 08/50] PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (6 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 07/50] PCI: endpoint: Add helper to get first unreserved BAR Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 09/50] PCI: pci-epf-test: Remove setting epf_bar flags in function driver Lad Prabhakar
                   ` (43 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1237 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 5544d67ed11245ccb64099deb32831308297bf6b upstream.

pci_epf_alloc_space() sets the MEM TYPE flags to indicate a 32-bit
Base Address Register irrespective of the size. Fix it here to indicate
64-bit BAR if the size is > 2GB.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epf-core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 825fa24427a3..8bfdcd291196 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -131,7 +131,9 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
 	epf->bar[bar].phys_addr = phys_addr;
 	epf->bar[bar].size = size;
 	epf->bar[bar].barno = bar;
-	epf->bar[bar].flags = PCI_BASE_ADDRESS_SPACE_MEMORY;
+	epf->bar[bar].flags |= upper_32_bits(size) ?
+				PCI_BASE_ADDRESS_MEM_TYPE_64 :
+				PCI_BASE_ADDRESS_MEM_TYPE_32;
 
 	return space;
 }
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 09/50] PCI: pci-epf-test: Remove setting epf_bar flags in function driver
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (7 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 08/50] PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 10/50] PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit Lad Prabhakar
                   ` (42 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1227 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 0342e9a797db42a7d4d083d10b5d3f38b0cfc193 upstream.

Now that pci_epf_alloc_space() sets BAR MEM TYPE flags as 64Bit or
32Bit based on size, remove setting it in function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 4bbd26e8a9e2..ad0efa4446ba 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -406,10 +406,6 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 	for (bar = BAR_0; bar <= BAR_5; bar++) {
 		epf_bar = &epf->bar[bar];
 
-		epf_bar->flags |= upper_32_bits(epf_bar->size) ?
-			PCI_BASE_ADDRESS_MEM_TYPE_64 :
-			PCI_BASE_ADDRESS_MEM_TYPE_32;
-
 		ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
 		if (ret) {
 			pci_epf_free_space(epf, epf_test->reg[bar], bar);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 10/50] PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (8 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 09/50] PCI: pci-epf-test: Remove setting epf_bar flags in function driver Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 11/50] PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features Lad Prabhakar
                   ` (41 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1713 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit b866c56b66d88a632e2fa6b922c4ea051937acbd upstream.

It's useless to allocate memory for next BAR if the current BAR is a
64Bit BAR. Stop allocating memory for the next BAR, if the current
BARs flag indicates this is a 64Bit BAR.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index ad0efa4446ba..a385927a9239 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -429,6 +429,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 	struct device *dev = &epf->dev;
+	struct pci_epf_bar *epf_bar;
 	void *base;
 	int bar;
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
@@ -442,6 +443,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	epf_test->reg[test_reg_bar] = base;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++) {
+		epf_bar = &epf->bar[bar];
 		if (bar == test_reg_bar)
 			continue;
 		base = pci_epf_alloc_space(epf, bar_size[bar], bar);
@@ -449,6 +451,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 			dev_err(dev, "Failed to allocate space for BAR%d\n",
 				bar);
 		epf_test->reg[bar] = base;
+		if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
+			bar++;
 	}
 
 	return 0;
-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 11/50] PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (9 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 10/50] PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 12/50] PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver Lad Prabhakar
                   ` (40 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 6439 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 2c04c5b8eef797dca99699cfb55ff42dd3c12c23 upstream.

Use pci_epc_get_features() to get EPC features such as linkup
notifier support, MSI/MSIX capable, BAR configuration etc and use it
for configuring pci-epf-test. Since these features are now obtained
directly from EPC driver, remove pci_epf_test_data which was initially
added to have EPC features in endpoint function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 87 ++++++++++++-------
 1 file changed, 54 insertions(+), 33 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index a385927a9239..d0b91da49bf4 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -47,9 +47,8 @@ struct pci_epf_test {
 	void			*reg[6];
 	struct pci_epf		*epf;
 	enum pci_barno		test_reg_bar;
-	bool			linkup_notifier;
-	bool			msix_available;
 	struct delayed_work	cmd_handler;
+	const struct pci_epc_features *epc_features;
 };
 
 struct pci_epf_test_reg {
@@ -71,11 +70,6 @@ static struct pci_epf_header test_header = {
 	.interrupt_pin	= PCI_INTERRUPT_INTA,
 };
 
-struct pci_epf_test_data {
-	enum pci_barno	test_reg_bar;
-	bool		linkup_notifier;
-};
-
 static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
 
 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
@@ -402,10 +396,16 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 	struct device *dev = &epf->dev;
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
+	const struct pci_epc_features *epc_features;
+
+	epc_features = epf_test->epc_features;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++) {
 		epf_bar = &epf->bar[bar];
 
+		if (!!(epc_features->reserved_bar & (1 << bar)))
+			continue;
+
 		ret = pci_epc_set_bar(epc, epf->func_no, epf_bar);
 		if (ret) {
 			pci_epf_free_space(epf, epf_test->reg[bar], bar);
@@ -433,6 +433,9 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	void *base;
 	int bar;
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
+	const struct pci_epc_features *epc_features;
+
+	epc_features = epf_test->epc_features;
 
 	base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
 				   test_reg_bar);
@@ -446,6 +449,10 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 		epf_bar = &epf->bar[bar];
 		if (bar == test_reg_bar)
 			continue;
+
+		if (!!(epc_features->reserved_bar & (1 << bar)))
+			continue;
+
 		base = pci_epf_alloc_space(epf, bar_size[bar], bar);
 		if (!base)
 			dev_err(dev, "Failed to allocate space for BAR%d\n",
@@ -458,25 +465,50 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	return 0;
 }
 
+static void pci_epf_configure_bar(struct pci_epf *epf,
+				  const struct pci_epc_features *epc_features)
+{
+	struct pci_epf_bar *epf_bar;
+	bool bar_fixed_64bit;
+	int i;
+
+	for (i = BAR_0; i <= BAR_5; i++) {
+		epf_bar = &epf->bar[i];
+		bar_fixed_64bit = !!(epc_features->bar_fixed_64bit & (1 << i));
+		if (bar_fixed_64bit)
+			epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
+		if (epc_features->bar_fixed_size[i])
+			bar_size[i] = epc_features->bar_fixed_size[i];
+	}
+}
+
 static int pci_epf_test_bind(struct pci_epf *epf)
 {
 	int ret;
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 	struct pci_epf_header *header = epf->header;
+	const struct pci_epc_features *epc_features;
+	enum pci_barno test_reg_bar = BAR_0;
 	struct pci_epc *epc = epf->epc;
 	struct device *dev = &epf->dev;
+	bool linkup_notifier = false;
+	bool msix_capable = false;
+	bool msi_capable = true;
 
 	if (WARN_ON_ONCE(!epc))
 		return -EINVAL;
 
-	if (epc->features & EPC_FEATURE_NO_LINKUP_NOTIFIER)
-		epf_test->linkup_notifier = false;
-	else
-		epf_test->linkup_notifier = true;
-
-	epf_test->msix_available = epc->features & EPC_FEATURE_MSIX_AVAILABLE;
+	epc_features = pci_epc_get_features(epc, epf->func_no);
+	if (epc_features) {
+		linkup_notifier = epc_features->linkup_notifier;
+		msix_capable = epc_features->msix_capable;
+		msi_capable = epc_features->msi_capable;
+		test_reg_bar = pci_epc_get_first_free_bar(epc_features);
+		pci_epf_configure_bar(epf, epc_features);
+	}
 
-	epf_test->test_reg_bar = EPC_FEATURE_GET_BAR(epc->features);
+	epf_test->test_reg_bar = test_reg_bar;
+	epf_test->epc_features = epc_features;
 
 	ret = pci_epc_write_header(epc, epf->func_no, header);
 	if (ret) {
@@ -492,13 +524,15 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	if (ret)
 		return ret;
 
-	ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
-	if (ret) {
-		dev_err(dev, "MSI configuration failed\n");
-		return ret;
+	if (msi_capable) {
+		ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
+		if (ret) {
+			dev_err(dev, "MSI configuration failed\n");
+			return ret;
+		}
 	}
 
-	if (epf_test->msix_available) {
+	if (msix_capable) {
 		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
 		if (ret) {
 			dev_err(dev, "MSI-X configuration failed\n");
@@ -506,7 +540,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 		}
 	}
 
-	if (!epf_test->linkup_notifier)
+	if (!linkup_notifier)
 		queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
 
 	return 0;
@@ -523,17 +557,6 @@ static int pci_epf_test_probe(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test;
 	struct device *dev = &epf->dev;
-	const struct pci_epf_device_id *match;
-	struct pci_epf_test_data *data;
-	enum pci_barno test_reg_bar = BAR_0;
-	bool linkup_notifier = true;
-
-	match = pci_epf_match_device(pci_epf_test_ids, epf);
-	data = (struct pci_epf_test_data *)match->driver_data;
-	if (data) {
-		test_reg_bar = data->test_reg_bar;
-		linkup_notifier = data->linkup_notifier;
-	}
 
 	epf_test = devm_kzalloc(dev, sizeof(*epf_test), GFP_KERNEL);
 	if (!epf_test)
@@ -541,8 +564,6 @@ static int pci_epf_test_probe(struct pci_epf *epf)
 
 	epf->header = &test_header;
 	epf_test->epf = epf;
-	epf_test->test_reg_bar = test_reg_bar;
-	epf_test->linkup_notifier = linkup_notifier;
 
 	INIT_DELAYED_WORK(&epf_test->cmd_handler, pci_epf_test_cmd_handler);
 
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 12/50] PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (10 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 11/50] PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 13/50] PCI: rockchip: Remove pci_epf_linkup() from Rockchip " Lad Prabhakar
                   ` (39 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit c274c9f4ea758bd6667a363f275e45275f2b5672 upstream.

pci_epf_linkup() is intended to be invoked if the EPC supports linkup
notification. Now that pci-epf-test uses the get_features() callback,
which indicates Cadence EP driver doesn't support the linkup notification,
remove pci_epf_linkup() from Cadence EP driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-cadence-ep.c | 12 ------------
 1 file changed, 12 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index 14c2545bb17e..def7820cb824 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -396,18 +396,6 @@ static int cdns_pcie_ep_start(struct pci_epc *epc)
 		cfg |= BIT(epf->func_no);
 	cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
 
-	/*
-	 * The PCIe links are automatically established by the controller
-	 * once for all at powerup: the software can neither start nor stop
-	 * those links later at runtime.
-	 *
-	 * Then we only have to notify the EP core that our links are already
-	 * established. However we don't call directly pci_epc_linkup() because
-	 * we've already locked the epc->lock.
-	 */
-	list_for_each_entry(epf, &epc->pci_epf, list)
-		pci_epf_linkup(epf);
-
 	return 0;
 }
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 13/50] PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (11 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 12/50] PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 14/50] PCI: designware-plat: Remove setting epc->features in Designware plat " Lad Prabhakar
                   ` (38 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1221 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit f1267978457e77ae7ddabe82ad48cf34f54e96fb upstream.

pci_epf_linkup() is intended to be invoked if the EPC supports linkup
notification. Now that pci-epf-test uses get_features callback, which
indicates Rockchip EP driver doesn't support linkup notification, remove
pci_epf_linkup() from Rockchip EP driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-rockchip-ep.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index ab6478334101..d743b0a48988 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -499,9 +499,6 @@ static int rockchip_pcie_ep_start(struct pci_epc *epc)
 
 	rockchip_pcie_write(rockchip, cfg, PCIE_CORE_PHY_FUNC_CFG);
 
-	list_for_each_entry(epf, &epc->pci_epf, list)
-		pci_epf_linkup(epf);
-
 	return 0;
 }
 
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 14/50] PCI: designware-plat: Remove setting epc->features in Designware plat EP driver
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (12 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 13/50] PCI: rockchip: Remove pci_epf_linkup() from Rockchip " Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 15/50] PCI: endpoint: Remove features member in struct pci_epc Lad Prabhakar
                   ` (37 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1489 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 92f2b028418c6f59f92703eed111136ca0d22c39 upstream.

Now that pci-epf-test uses get_features callback and
dw_plat_pcie_epc_features in Designware plat EP driver already indicates
it doesn't support linkup notification and is MSIX capable, remove setting
epc->features which is not used anymore by the endpoint function driver.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/dwc/pcie-designware-plat.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index bd0516afc86f..3be87126aef3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -70,14 +70,10 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	struct pci_epc *epc = ep->epc;
 	enum pci_barno bar;
 
 	for (bar = BAR_0; bar <= BAR_5; bar++)
 		dw_pcie_ep_reset_bar(pci, bar);
-
-	epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER;
-	epc->features |= EPC_FEATURE_MSIX_AVAILABLE;
 }
 
 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 15/50] PCI: endpoint: Remove features member in struct pci_epc
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (13 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 14/50] PCI: designware-plat: Remove setting epc->features in Designware plat " Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 16/50] PCI: endpoint: Fix a potential NULL pointer dereference Lad Prabhakar
                   ` (36 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1558 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 35ce0d7922d68021062a955407740d262f9ac811 upstream.

Since EPC features are now implemented using pci_epc_features and
all the EPC drivers are moved to using pci_epc_features, remove
features member in struct pci_epc and all the helper macros for
configuring the features.

Tested-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/linux/pci-epc.h | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index dcaecf715b1c..b3a3c0805603 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -102,7 +102,6 @@ struct pci_epc {
 	struct config_group		*group;
 	/* spinlock to protect against concurrent access of EP controller */
 	spinlock_t			lock;
-	unsigned int			features;
 };
 
 /**
@@ -123,14 +122,6 @@ struct pci_epc_features {
 	u64	bar_fixed_size[BAR_5 + 1];
 };
 
-#define EPC_FEATURE_NO_LINKUP_NOTIFIER		BIT(0)
-#define EPC_FEATURE_BAR_MASK			(BIT(1) | BIT(2) | BIT(3))
-#define EPC_FEATURE_MSIX_AVAILABLE		BIT(4)
-#define EPC_FEATURE_SET_BAR(features, bar)	\
-		(features |= (EPC_FEATURE_BAR_MASK & (bar << 1)))
-#define EPC_FEATURE_GET_BAR(features)		\
-		((features & EPC_FEATURE_BAR_MASK) >> 1)
-
 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
 
 #define pci_epc_create(dev, ops)    \
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 16/50] PCI: endpoint: Fix a potential NULL pointer dereference
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (14 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 15/50] PCI: endpoint: Remove features member in struct pci_epc Lad Prabhakar
@ 2020-10-12 14:18 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 17/50] PCI: endpoint: Add support to specify alignment for buffers allocated to BARs Lad Prabhakar
                   ` (35 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:18 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1174 bytes --]

From: Kangjie Lu <kjlu@umn.edu>

commit 507b820009a457afa78202da337bcb56791fbb12 upstream.

In case alloc_workqueue() fails, return -ENOMEM to avoid
potential NULL pointer dereferences.

Signed-off-by: Kangjie Lu <kjlu@umn.edu>
[lorenzo.pieralisi@arm.com: commit log and code update]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index d0b91da49bf4..ed5cd28b9572 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -591,6 +591,11 @@ static int __init pci_epf_test_init(void)
 
 	kpcitest_workqueue = alloc_workqueue("kpcitest",
 					     WQ_MEM_RECLAIM | WQ_HIGHPRI, 0);
+	if (!kpcitest_workqueue) {
+		pr_err("Failed to allocate the kpcitest work queue\n");
+		return -ENOMEM;
+	}
+
 	ret = pci_epf_register_driver(&test_driver);
 	if (ret) {
 		pr_err("Failed to register pci epf test driver --> %d\n", ret);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 17/50] PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (15 preceding siblings ...)
  2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 16/50] PCI: endpoint: Fix a potential NULL pointer dereference Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 18/50] PCI: endpoint: Set endpoint controller pointer to NULL Lad Prabhakar
                   ` (34 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 5289 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 2a9a801620efac92885fc9cd53594c0b9aba87a4 upstream.

The address that is allocated using pci_epf_alloc_space() is
directly written to the target address of the Inbound Address
Translation unit (ie the HW component implementing inbound address
decoding) on endpoint controllers.

Designware IP [1] has a configuration parameter (CX_ATU_MIN_REGION_SIZE
[2]) which has 64KB as default value and the lower 16 bits of the Base,
Limit and Target registers of the Inbound ATU are fixed to zero. If the
programmed memory address is not aligned to 64 KB boundary this causes
memory corruption.

Modify pci_epf_alloc_space() API to take alignment size as argument in
order to allocate buffers to be mapped to BARs with an alignment that
suits the platform where they are used.

Add an 'align' parameter to epc_features which can be used by platform
drivers to specify the BAR allocation alignment requirements and use
this while invoking pci_epf_alloc_space().

[1] "I/O and MEM Match Modes" section in DesignWare Cores PCI Express
     Controller Databook version 4.90a
[2]  http://www.ti.com/lit/ug/spruid7c/spruid7c.pdf

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c |  5 +++--
 drivers/pci/endpoint/pci-epf-core.c           | 10 ++++++++--
 include/linux/pci-epc.h                       |  2 ++
 include/linux/pci-epf.h                       |  3 ++-
 4 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index ed5cd28b9572..27806987e93b 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -438,7 +438,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	epc_features = epf_test->epc_features;
 
 	base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
-				   test_reg_bar);
+				   test_reg_bar, epc_features->align);
 	if (!base) {
 		dev_err(dev, "Failed to allocated register space\n");
 		return -ENOMEM;
@@ -453,7 +453,8 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 		if (!!(epc_features->reserved_bar & (1 << bar)))
 			continue;
 
-		base = pci_epf_alloc_space(epf, bar_size[bar], bar);
+		base = pci_epf_alloc_space(epf, bar_size[bar], bar,
+					   epc_features->align);
 		if (!base)
 			dev_err(dev, "Failed to allocate space for BAR%d\n",
 				bar);
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 8bfdcd291196..fb1306de8f40 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -109,10 +109,12 @@ EXPORT_SYMBOL_GPL(pci_epf_free_space);
  * pci_epf_alloc_space() - allocate memory for the PCI EPF register space
  * @size: the size of the memory that has to be allocated
  * @bar: the BAR number corresponding to the allocated register space
+ * @align: alignment size for the allocation region
  *
  * Invoke to allocate memory for the PCI EPF register space.
  */
-void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
+			  size_t align)
 {
 	void *space;
 	struct device *dev = epf->epc->dev.parent;
@@ -120,7 +122,11 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar)
 
 	if (size < 128)
 		size = 128;
-	size = roundup_pow_of_two(size);
+
+	if (align)
+		size = ALIGN(size, align);
+	else
+		size = roundup_pow_of_two(size);
 
 	space = dma_alloc_coherent(dev, size, &phys_addr, GFP_KERNEL);
 	if (!space) {
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index b3a3c0805603..0c12d69dde92 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -112,6 +112,7 @@ struct pci_epc {
  * @reserved_bar: bitmap to indicate reserved BAR unavailable to function driver
  * @bar_fixed_64bit: bitmap to indicate fixed 64bit BARs
  * @bar_fixed_size: Array specifying the size supported by each BAR
+ * @align: alignment size required for BAR buffer allocation
  */
 struct pci_epc_features {
 	unsigned int	linkup_notifier : 1;
@@ -120,6 +121,7 @@ struct pci_epc_features {
 	u8	reserved_bar;
 	u8	bar_fixed_64bit;
 	u64	bar_fixed_size[BAR_5 + 1];
+	size_t	align;
 };
 
 #define to_pci_epc(device) container_of((device), struct pci_epc, dev)
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index ec02f58758c8..2d6f07556682 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -149,7 +149,8 @@ void pci_epf_destroy(struct pci_epf *epf);
 int __pci_epf_register_driver(struct pci_epf_driver *driver,
 			      struct module *owner);
 void pci_epf_unregister_driver(struct pci_epf_driver *driver);
-void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar);
+void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
+			  size_t align);
 void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
 int pci_epf_bind(struct pci_epf *epf);
 void pci_epf_unbind(struct pci_epf *epf);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 18/50] PCI: endpoint: Set endpoint controller pointer to NULL
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (16 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 17/50] PCI: endpoint: Add support to specify alignment for buffers allocated to BARs Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 19/50] PCI: endpoint: Allocate enough space for fixed size BAR Lad Prabhakar
                   ` (33 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1190 bytes --]

From: Alan Mikhak <alan.mikhak@sifive.com>

commit db7a62482d2f6a63f36f30f62c4cbf1e53035719 upstream.

Set endpoint controller pointer to NULL in pci_epc_remove_epf()
to avoid -EBUSY on subsequent call to pci_epc_add_epf().

Add a check for NULL endpoint function pointer.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index e4712a0f249c..2091508c1620 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -519,11 +519,12 @@ void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
 	unsigned long flags;
 
-	if (!epc || IS_ERR(epc))
+	if (!epc || IS_ERR(epc) || !epf)
 		return;
 
 	spin_lock_irqsave(&epc->lock, flags);
 	list_del(&epf->list);
+	epf->epc = NULL;
 	spin_unlock_irqrestore(&epc->lock, flags);
 }
 EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 19/50] PCI: endpoint: Allocate enough space for fixed size BAR
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (17 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 18/50] PCI: endpoint: Set endpoint controller pointer to NULL Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 20/50] PCI: endpoint: Skip odd BAR when skipping 64bit BAR Lad Prabhakar
                   ` (32 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1652 bytes --]

From: Alan Mikhak <alan.mikhak@sifive.com>

commit f16fb16ed16c7f561e9c41c9ae4107c7f6aa553c upstream.

PCI endpoint test function code should honor the .bar_fixed_size parameter
from underlying endpoint controller drivers or results may be unexpected.

In pci_epf_test_alloc_space(), check if BAR being used for test
register space is a fixed size BAR. If so, allocate the required fixed
size.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 27806987e93b..7d41e6684b87 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -434,10 +434,16 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	int bar;
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
 	const struct pci_epc_features *epc_features;
+	size_t test_reg_size;
 
 	epc_features = epf_test->epc_features;
 
-	base = pci_epf_alloc_space(epf, sizeof(struct pci_epf_test_reg),
+	if (epc_features->bar_fixed_size[test_reg_bar])
+		test_reg_size = bar_size[test_reg_bar];
+	else
+		test_reg_size = sizeof(struct pci_epf_test_reg);
+
+	base = pci_epf_alloc_space(epf, test_reg_size,
 				   test_reg_bar, epc_features->align);
 	if (!base) {
 		dev_err(dev, "Failed to allocated register space\n");
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 20/50] PCI: endpoint: Skip odd BAR when skipping 64bit BAR
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (18 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 19/50] PCI: endpoint: Allocate enough space for fixed size BAR Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 21/50] PCI: endpoint: Clear BAR before freeing its space Lad Prabhakar
                   ` (31 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 3278 bytes --]

From: Alan Mikhak <alan.mikhak@sifive.com>

commit 3041a643613a2530ade35a9ae97709a9da4c0c72 upstream.

Always skip odd BAR when skipping 64bit BARs in pci_epf_test_set_bar()
and pci_epf_test_alloc_space() otherwise pci_epf_test_set_bar() will
call pci_epc_set_bar() on an odd loop index when skipping reserved 64bit
BAR.

Moreover, pci_epf_test_alloc_space() will call pci_epf_alloc_space() on
bind for an odd loop index when BAR is 64bit but leaks on subsequent
unbind by not calling pci_epf_free_space().

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 25 +++++++++----------
 1 file changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 7d41e6684b87..e8bcc924dbf8 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -389,7 +389,7 @@ static void pci_epf_test_unbind(struct pci_epf *epf)
 
 static int pci_epf_test_set_bar(struct pci_epf *epf)
 {
-	int bar;
+	int bar, add;
 	int ret;
 	struct pci_epf_bar *epf_bar;
 	struct pci_epc *epc = epf->epc;
@@ -400,8 +400,14 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 
 	epc_features = epf_test->epc_features;
 
-	for (bar = BAR_0; bar <= BAR_5; bar++) {
+	for (bar = BAR_0; bar <= BAR_5; bar += add) {
 		epf_bar = &epf->bar[bar];
+		/*
+		 * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
+		 * if the specific implementation required a 64-bit BAR,
+		 * even if we only requested a 32-bit BAR.
+		 */
+		add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
 
 		if (!!(epc_features->reserved_bar & (1 << bar)))
 			continue;
@@ -413,13 +419,6 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 			if (bar == test_reg_bar)
 				return ret;
 		}
-		/*
-		 * pci_epc_set_bar() sets PCI_BASE_ADDRESS_MEM_TYPE_64
-		 * if the specific implementation required a 64-bit BAR,
-		 * even if we only requested a 32-bit BAR.
-		 */
-		if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
-			bar++;
 	}
 
 	return 0;
@@ -431,7 +430,7 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	struct device *dev = &epf->dev;
 	struct pci_epf_bar *epf_bar;
 	void *base;
-	int bar;
+	int bar, add;
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
 	const struct pci_epc_features *epc_features;
 	size_t test_reg_size;
@@ -451,8 +450,10 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	}
 	epf_test->reg[test_reg_bar] = base;
 
-	for (bar = BAR_0; bar <= BAR_5; bar++) {
+	for (bar = BAR_0; bar <= BAR_5; bar += add) {
 		epf_bar = &epf->bar[bar];
+		add = (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64) ? 2 : 1;
+
 		if (bar == test_reg_bar)
 			continue;
 
@@ -465,8 +466,6 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 			dev_err(dev, "Failed to allocate space for BAR%d\n",
 				bar);
 		epf_test->reg[bar] = base;
-		if (epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
-			bar++;
 	}
 
 	return 0;
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 21/50] PCI: endpoint: Clear BAR before freeing its space
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (19 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 20/50] PCI: endpoint: Skip odd BAR when skipping 64bit BAR Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 22/50] PCI: endpoint: Cast the page number to phys_addr_t Lad Prabhakar
                   ` (30 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1351 bytes --]

From: Alan Mikhak <alan.mikhak@sifive.com>

commit dbb7bbcc8ad248b1ab05bd27dfdb587ef4023dab upstream.

Associated pci_epf_bar structure is needed in pci_epc_clear_bar() to
clear a BAR correctly but it is reset in pci_epf_free_space() (that
is called first) which results in pci_epc_clear_bar() failure.

Reorder the pci_epc_clear_bar()/pci_epf_free_space() calls execution
to fix the issue.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
[lorenzo.pieralisi@arm.com: reworded the commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index e8bcc924dbf8..1cfe3687a211 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -381,8 +381,8 @@ static void pci_epf_test_unbind(struct pci_epf *epf)
 		epf_bar = &epf->bar[bar];
 
 		if (epf_test->reg[bar]) {
-			pci_epf_free_space(epf, epf_test->reg[bar], bar);
 			pci_epc_clear_bar(epc, epf->func_no, epf_bar);
+			pci_epf_free_space(epf, epf_test->reg[bar], bar);
 		}
 	}
 }
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 22/50] PCI: endpoint: Cast the page number to phys_addr_t
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (20 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 21/50] PCI: endpoint: Clear BAR before freeing its space Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 23/50] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Lad Prabhakar
                   ` (29 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1426 bytes --]

From: Alan Mikhak <alan.mikhak@sifive.com>

commit daee4f4e42c792997f4fee47dcdfa65dd720ec02 upstream.

Modify pci_epc_mem_alloc_addr() to cast the variable 'pageno'
from type 'int' to 'phys_addr_t' before shifting left. This
cast is needed to avoid treating bit 31 of 'pageno' as the
sign bit which would otherwise get sign-extended to produce
a negative value. When added to the base address of PCI memory
space, the negative value would produce an invalid physical
address which falls before the start of the PCI memory space.

Signed-off-by: Alan Mikhak <alan.mikhak@sifive.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-mem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c
index 0471643cf536..abfac1109a13 100644
--- a/drivers/pci/endpoint/pci-epc-mem.c
+++ b/drivers/pci/endpoint/pci-epc-mem.c
@@ -136,7 +136,7 @@ void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
 	if (pageno < 0)
 		goto ret;
 
-	*phys_addr = mem->phys_base + (pageno << page_shift);
+	*phys_addr = mem->phys_base + ((phys_addr_t)pageno << page_shift);
 	virt_addr = ioremap(*phys_addr, size);
 	if (!virt_addr)
 		bitmap_release_region(mem->bitmap, pageno, order);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 23/50] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (21 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 22/50] PCI: endpoint: Cast the page number to phys_addr_t Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex Lad Prabhakar
                   ` (28 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 7363 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 5779dd0a7dbd71e82478fb0bf125cc6cd3c43266 upstream.

Use atomic_notifier_call_chain() to notify EPC events like linkup to EPF
driver instead of using linkup ops in EPF driver. This is in preparation
for adding proper locking mechanism to EPF ops. This will also enable to
add more events (in addition to linkup) in the future.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 13 ++++++++---
 drivers/pci/endpoint/pci-epc-core.c           |  9 ++------
 drivers/pci/endpoint/pci-epf-core.c           | 22 +------------------
 include/linux/pci-epc.h                       |  8 +++++++
 include/linux/pci-epf.h                       |  6 ++---
 5 files changed, 23 insertions(+), 35 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 1cfe3687a211..7dd40ab8b5d2 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -360,12 +360,16 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
 			   msecs_to_jiffies(1));
 }
 
-static void pci_epf_test_linkup(struct pci_epf *epf)
+static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
+				 void *data)
 {
+	struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 
 	queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
 			   msecs_to_jiffies(1));
+
+	return NOTIFY_OK;
 }
 
 static void pci_epf_test_unbind(struct pci_epf *epf)
@@ -546,8 +550,12 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 		}
 	}
 
-	if (!linkup_notifier)
+	if (linkup_notifier) {
+		epf->nb.notifier_call = pci_epf_test_notifier;
+		pci_epc_register_notifier(epc, &epf->nb);
+	} else {
 		queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work);
+	}
 
 	return 0;
 }
@@ -580,7 +588,6 @@ static int pci_epf_test_probe(struct pci_epf *epf)
 static struct pci_epf_ops ops = {
 	.unbind	= pci_epf_test_unbind,
 	.bind	= pci_epf_test_bind,
-	.linkup = pci_epf_test_linkup,
 };
 
 static struct pci_epf_driver test_driver = {
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 2091508c1620..2f6436599fcb 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -539,16 +539,10 @@ EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
  */
 void pci_epc_linkup(struct pci_epc *epc)
 {
-	unsigned long flags;
-	struct pci_epf *epf;
-
 	if (!epc || IS_ERR(epc))
 		return;
 
-	spin_lock_irqsave(&epc->lock, flags);
-	list_for_each_entry(epf, &epc->pci_epf, list)
-		pci_epf_linkup(epf);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	atomic_notifier_call_chain(&epc->notifier, 0, NULL);
 }
 EXPORT_SYMBOL_GPL(pci_epc_linkup);
 
@@ -612,6 +606,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
 
 	spin_lock_init(&epc->lock);
 	INIT_LIST_HEAD(&epc->pci_epf);
+	ATOMIC_INIT_NOTIFIER_HEAD(&epc->notifier);
 
 	device_initialize(&epc->dev);
 	epc->dev.class = pci_epc_class;
diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index fb1306de8f40..93f28c65ace0 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -20,26 +20,6 @@ static DEFINE_MUTEX(pci_epf_mutex);
 static struct bus_type pci_epf_bus_type;
 static const struct device_type pci_epf_type;
 
-/**
- * pci_epf_linkup() - Notify the function driver that EPC device has
- *		      established a connection with the Root Complex.
- * @epf: the EPF device bound to the EPC device which has established
- *	 the connection with the host
- *
- * Invoke to notify the function driver that EPC device has established
- * a connection with the Root Complex.
- */
-void pci_epf_linkup(struct pci_epf *epf)
-{
-	if (!epf->driver) {
-		dev_WARN(&epf->dev, "epf device not bound to driver\n");
-		return;
-	}
-
-	epf->driver->ops->linkup(epf);
-}
-EXPORT_SYMBOL_GPL(pci_epf_linkup);
-
 /**
  * pci_epf_unbind() - Notify the function driver that the binding between the
  *		      EPF device and EPC device has been lost
@@ -214,7 +194,7 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver,
 	if (!driver->ops)
 		return -EINVAL;
 
-	if (!driver->ops->bind || !driver->ops->unbind || !driver->ops->linkup)
+	if (!driver->ops->bind || !driver->ops->unbind)
 		return -EINVAL;
 
 	driver->driver.bus = &pci_epf_bus_type;
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 0c12d69dde92..8c61908d2c41 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -92,6 +92,7 @@ struct pci_epc_mem {
  * @max_functions: max number of functions that can be configured in this EPC
  * @group: configfs group representing the PCI EPC device
  * @lock: spinlock to protect pci_epc ops
+ * @notifier: used to notify EPF of any EPC events (like linkup)
  */
 struct pci_epc {
 	struct device			dev;
@@ -102,6 +103,7 @@ struct pci_epc {
 	struct config_group		*group;
 	/* spinlock to protect against concurrent access of EP controller */
 	spinlock_t			lock;
+	struct atomic_notifier_head	notifier;
 };
 
 /**
@@ -144,6 +146,12 @@ static inline void *epc_get_drvdata(struct pci_epc *epc)
 	return dev_get_drvdata(&epc->dev);
 }
 
+static inline int
+pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb)
+{
+	return atomic_notifier_chain_register(&epc->notifier, nb);
+}
+
 struct pci_epc *
 __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
 		      struct module *owner);
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 2d6f07556682..4993f7f6439b 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -55,13 +55,10 @@ struct pci_epf_header {
  * @bind: ops to perform when a EPC device has been bound to EPF device
  * @unbind: ops to perform when a binding has been lost between a EPC device
  *	    and EPF device
- * @linkup: ops to perform when the EPC device has established a connection with
- *	    a host system
  */
 struct pci_epf_ops {
 	int	(*bind)(struct pci_epf *epf);
 	void	(*unbind)(struct pci_epf *epf);
-	void	(*linkup)(struct pci_epf *epf);
 };
 
 /**
@@ -112,6 +109,7 @@ struct pci_epf_bar {
  * @epc: the EPC device to which this EPF device is bound
  * @driver: the EPF driver to which this EPF device is bound
  * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc
+ * @nb: notifier block to notify EPF of any EPC events (like linkup)
  */
 struct pci_epf {
 	struct device		dev;
@@ -125,6 +123,7 @@ struct pci_epf {
 	struct pci_epc		*epc;
 	struct pci_epf_driver	*driver;
 	struct list_head	list;
+	struct notifier_block   nb;
 };
 
 #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
@@ -154,5 +153,4 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
 void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar);
 int pci_epf_bind(struct pci_epf *epf);
 void pci_epf_unbind(struct pci_epf *epf);
-void pci_epf_linkup(struct pci_epf *epf);
 #endif /* __LINUX_PCI_EPF_H */
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (22 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 23/50] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-20 20:43   ` Pavel Machek
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 25/50] PCI: endpoint: Protect concurrent access to pci_epf_ops " Lad Prabhakar
                   ` (27 subsequent siblings)
  51 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 10278 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 3d3248dbd018502f654064c78efcd2e165ab3486 upstream.

The pci_epc_ops is not intended to be invoked from interrupt context.
Hence replace spin_lock_irqsave and spin_unlock_irqrestore with
mutex_lock and mutex_unlock respectively.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-core.c | 82 +++++++++++------------------
 include/linux/pci-epc.h             |  6 +--
 2 files changed, 34 insertions(+), 54 deletions(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 2f6436599fcb..e51a12ed85bb 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -120,7 +120,6 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
 						    u8 func_no)
 {
 	const struct pci_epc_features *epc_features;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return NULL;
@@ -128,9 +127,9 @@ const struct pci_epc_features *pci_epc_get_features(struct pci_epc *epc,
 	if (!epc->ops->get_features)
 		return NULL;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	epc_features = epc->ops->get_features(epc, func_no);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return epc_features;
 }
@@ -144,14 +143,12 @@ EXPORT_SYMBOL_GPL(pci_epc_get_features);
  */
 void pci_epc_stop(struct pci_epc *epc)
 {
-	unsigned long flags;
-
 	if (IS_ERR(epc) || !epc->ops->stop)
 		return;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	epc->ops->stop(epc);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 }
 EXPORT_SYMBOL_GPL(pci_epc_stop);
 
@@ -164,7 +161,6 @@ EXPORT_SYMBOL_GPL(pci_epc_stop);
 int pci_epc_start(struct pci_epc *epc)
 {
 	int ret;
-	unsigned long flags;
 
 	if (IS_ERR(epc))
 		return -EINVAL;
@@ -172,9 +168,9 @@ int pci_epc_start(struct pci_epc *epc)
 	if (!epc->ops->start)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->start(epc);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -193,7 +189,6 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
 		      enum pci_epc_irq_type type, u16 interrupt_num)
 {
 	int ret;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return -EINVAL;
@@ -201,9 +196,9 @@ int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
 	if (!epc->ops->raise_irq)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->raise_irq(epc, func_no, type, interrupt_num);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -219,7 +214,6 @@ EXPORT_SYMBOL_GPL(pci_epc_raise_irq);
 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
 {
 	int interrupt;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return 0;
@@ -227,9 +221,9 @@ int pci_epc_get_msi(struct pci_epc *epc, u8 func_no)
 	if (!epc->ops->get_msi)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	interrupt = epc->ops->get_msi(epc, func_no);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	if (interrupt < 0)
 		return 0;
@@ -252,7 +246,6 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
 {
 	int ret;
 	u8 encode_int;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
 	    interrupts > 32)
@@ -263,9 +256,9 @@ int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts)
 
 	encode_int = order_base_2(interrupts);
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->set_msi(epc, func_no, encode_int);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -281,7 +274,6 @@ EXPORT_SYMBOL_GPL(pci_epc_set_msi);
 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
 {
 	int interrupt;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return 0;
@@ -289,9 +281,9 @@ int pci_epc_get_msix(struct pci_epc *epc, u8 func_no)
 	if (!epc->ops->get_msix)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	interrupt = epc->ops->get_msix(epc, func_no);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	if (interrupt < 0)
 		return 0;
@@ -311,7 +303,6 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msix);
 int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
 {
 	int ret;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
 	    interrupts < 1 || interrupts > 2048)
@@ -320,9 +311,9 @@ int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
 	if (!epc->ops->set_msix)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -339,17 +330,15 @@ EXPORT_SYMBOL_GPL(pci_epc_set_msix);
 void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
 			phys_addr_t phys_addr)
 {
-	unsigned long flags;
-
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return;
 
 	if (!epc->ops->unmap_addr)
 		return;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	epc->ops->unmap_addr(epc, func_no, phys_addr);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 }
 EXPORT_SYMBOL_GPL(pci_epc_unmap_addr);
 
@@ -367,7 +356,6 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
 		     phys_addr_t phys_addr, u64 pci_addr, size_t size)
 {
 	int ret;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return -EINVAL;
@@ -375,9 +363,9 @@ int pci_epc_map_addr(struct pci_epc *epc, u8 func_no,
 	if (!epc->ops->map_addr)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->map_addr(epc, func_no, phys_addr, pci_addr, size);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -394,8 +382,6 @@ EXPORT_SYMBOL_GPL(pci_epc_map_addr);
 void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
 		       struct pci_epf_bar *epf_bar)
 {
-	unsigned long flags;
-
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
 	    (epf_bar->barno == BAR_5 &&
 	     epf_bar->flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
@@ -404,9 +390,9 @@ void pci_epc_clear_bar(struct pci_epc *epc, u8 func_no,
 	if (!epc->ops->clear_bar)
 		return;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	epc->ops->clear_bar(epc, func_no, epf_bar);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 }
 EXPORT_SYMBOL_GPL(pci_epc_clear_bar);
 
@@ -422,7 +408,6 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
 		    struct pci_epf_bar *epf_bar)
 {
 	int ret;
-	unsigned long irq_flags;
 	int flags = epf_bar->flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions ||
@@ -437,9 +422,9 @@ int pci_epc_set_bar(struct pci_epc *epc, u8 func_no,
 	if (!epc->ops->set_bar)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, irq_flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->set_bar(epc, func_no, epf_bar);
-	spin_unlock_irqrestore(&epc->lock, irq_flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -460,7 +445,6 @@ int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
 			 struct pci_epf_header *header)
 {
 	int ret;
-	unsigned long flags;
 
 	if (IS_ERR_OR_NULL(epc) || func_no >= epc->max_functions)
 		return -EINVAL;
@@ -468,9 +452,9 @@ int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
 	if (!epc->ops->write_header)
 		return 0;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	ret = epc->ops->write_header(epc, func_no, header);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return ret;
 }
@@ -487,8 +471,6 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header);
  */
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
-	unsigned long flags;
-
 	if (epf->epc)
 		return -EBUSY;
 
@@ -500,9 +482,9 @@ int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
 
 	epf->epc = epc;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	list_add_tail(&epf->list, &epc->pci_epf);
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 
 	return 0;
 }
@@ -517,15 +499,13 @@ EXPORT_SYMBOL_GPL(pci_epc_add_epf);
  */
 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
-	unsigned long flags;
-
 	if (!epc || IS_ERR(epc) || !epf)
 		return;
 
-	spin_lock_irqsave(&epc->lock, flags);
+	mutex_lock(&epc->lock);
 	list_del(&epf->list);
 	epf->epc = NULL;
-	spin_unlock_irqrestore(&epc->lock, flags);
+	mutex_unlock(&epc->lock);
 }
 EXPORT_SYMBOL_GPL(pci_epc_remove_epf);
 
@@ -604,7 +584,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops,
 		goto err_ret;
 	}
 
-	spin_lock_init(&epc->lock);
+	mutex_init(&epc->lock);
 	INIT_LIST_HEAD(&epc->pci_epf);
 	ATOMIC_INIT_NOTIFIER_HEAD(&epc->notifier);
 
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 8c61908d2c41..9b21692bc2e4 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -91,7 +91,7 @@ struct pci_epc_mem {
  * @mem: address space of the endpoint controller
  * @max_functions: max number of functions that can be configured in this EPC
  * @group: configfs group representing the PCI EPC device
- * @lock: spinlock to protect pci_epc ops
+ * @lock: mutex to protect pci_epc ops
  * @notifier: used to notify EPF of any EPC events (like linkup)
  */
 struct pci_epc {
@@ -101,8 +101,8 @@ struct pci_epc {
 	struct pci_epc_mem		*mem;
 	u8				max_functions;
 	struct config_group		*group;
-	/* spinlock to protect against concurrent access of EP controller */
-	spinlock_t			lock;
+	/* mutex to protect against concurrent access of EP controller */
+	struct mutex			lock;
 	struct atomic_notifier_head	notifier;
 };
 
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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* [cip-dev] [RFC PATCH 4.19.y-cip 25/50] PCI: endpoint: Protect concurrent access to pci_epf_ops with mutex
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (23 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 26/50] PCI: endpoint: Assign function number for each PF in EPC core Lad Prabhakar
                   ` (26 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2503 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 07301c982643a432212840a4b648b5d3f5a061fa upstream.

Protect concurrent access to pci_epf_ops with a mutex.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epf-core.c | 11 ++++++++++-
 include/linux/pci-epf.h             |  3 +++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 93f28c65ace0..6e0648991b5c 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -35,7 +35,9 @@ void pci_epf_unbind(struct pci_epf *epf)
 		return;
 	}
 
+	mutex_lock(&epf->lock);
 	epf->driver->ops->unbind(epf);
+	mutex_unlock(&epf->lock);
 	module_put(epf->driver->owner);
 }
 EXPORT_SYMBOL_GPL(pci_epf_unbind);
@@ -49,6 +51,8 @@ EXPORT_SYMBOL_GPL(pci_epf_unbind);
  */
 int pci_epf_bind(struct pci_epf *epf)
 {
+	int ret;
+
 	if (!epf->driver) {
 		dev_WARN(&epf->dev, "epf device not bound to driver\n");
 		return -EINVAL;
@@ -57,7 +61,11 @@ int pci_epf_bind(struct pci_epf *epf)
 	if (!try_module_get(epf->driver->owner))
 		return -EAGAIN;
 
-	return epf->driver->ops->bind(epf);
+	mutex_lock(&epf->lock);
+	ret = epf->driver->ops->bind(epf);
+	mutex_unlock(&epf->lock);
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(pci_epf_bind);
 
@@ -252,6 +260,7 @@ struct pci_epf *pci_epf_create(const char *name)
 	device_initialize(dev);
 	dev->bus = &pci_epf_bus_type;
 	dev->type = &pci_epf_type;
+	mutex_init(&epf->lock);
 
 	ret = dev_set_name(dev, "%s", name);
 	if (ret) {
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 4993f7f6439b..bcdf4f07bde7 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -110,6 +110,7 @@ struct pci_epf_bar {
  * @driver: the EPF driver to which this EPF device is bound
  * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc
  * @nb: notifier block to notify EPF of any EPC events (like linkup)
+ * @lock: mutex to protect pci_epf_ops
  */
 struct pci_epf {
 	struct device		dev;
@@ -124,6 +125,8 @@ struct pci_epf {
 	struct pci_epf_driver	*driver;
 	struct list_head	list;
 	struct notifier_block   nb;
+	/* mutex to protect against concurrent access of pci_epf_ops */
+	struct mutex		lock;
 };
 
 #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 26/50] PCI: endpoint: Assign function number for each PF in EPC core
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (24 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 25/50] PCI: endpoint: Protect concurrent access to pci_epf_ops " Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 27/50] PCI: endpoint: Add core init notifying feature Lad Prabhakar
                   ` (25 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 4843 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 2499ee84e02774a8573b7b4c76c8f2ea38669313 upstream.

The PCIe endpoint core relies on the drivers that invoke the
pci_epc_add_epf() API to allocate and assign a function number
to each physical function (PF). Since endpoint function device can
be created by multiple mechanisms (configfs, devicetree, etc..),
allowing each of these mechanisms to assign a function number
would result in mutliple endpoint function devices having the
same function number. In order to avoid this, let EPC core assign
a function number to the endpoint device.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-ep-cfs.c   | 27 +++++----------------------
 drivers/pci/endpoint/pci-epc-core.c | 26 ++++++++++++++++++++++----
 include/linux/pci-epc.h             |  2 ++
 3 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index d1288a0bd530..e7e8367eead1 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -29,7 +29,6 @@ struct pci_epc_group {
 	struct config_group group;
 	struct pci_epc *epc;
 	bool start;
-	unsigned long function_num_map;
 };
 
 static inline struct pci_epf_group *to_pci_epf_group(struct config_item *item)
@@ -89,37 +88,22 @@ static int pci_epc_epf_link(struct config_item *epc_item,
 			    struct config_item *epf_item)
 {
 	int ret;
-	u32 func_no = 0;
 	struct pci_epf_group *epf_group = to_pci_epf_group(epf_item);
 	struct pci_epc_group *epc_group = to_pci_epc_group(epc_item);
 	struct pci_epc *epc = epc_group->epc;
 	struct pci_epf *epf = epf_group->epf;
 
-	func_no = find_first_zero_bit(&epc_group->function_num_map,
-				      BITS_PER_LONG);
-	if (func_no >= BITS_PER_LONG)
-		return -EINVAL;
-
-	set_bit(func_no, &epc_group->function_num_map);
-	epf->func_no = func_no;
-
 	ret = pci_epc_add_epf(epc, epf);
 	if (ret)
-		goto err_add_epf;
+		return ret;
 
 	ret = pci_epf_bind(epf);
-	if (ret)
-		goto err_epf_bind;
+	if (ret) {
+		pci_epc_remove_epf(epc, epf);
+		return ret;
+	}
 
 	return 0;
-
-err_epf_bind:
-	pci_epc_remove_epf(epc, epf);
-
-err_add_epf:
-	clear_bit(func_no, &epc_group->function_num_map);
-
-	return ret;
 }
 
 static void pci_epc_epf_unlink(struct config_item *epc_item,
@@ -134,7 +118,6 @@ static void pci_epc_epf_unlink(struct config_item *epc_item,
 
 	epc = epc_group->epc;
 	epf = epf_group->epf;
-	clear_bit(epf->func_no, &epc_group->function_num_map);
 	pci_epf_unbind(epf);
 	pci_epc_remove_epf(epc, epf);
 }
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index e51a12ed85bb..dc1c673534e0 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -471,22 +471,39 @@ EXPORT_SYMBOL_GPL(pci_epc_write_header);
  */
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf)
 {
+	u32 func_no;
+	int ret = 0;
+
 	if (epf->epc)
 		return -EBUSY;
 
 	if (IS_ERR(epc))
 		return -EINVAL;
 
-	if (epf->func_no > epc->max_functions - 1)
-		return -EINVAL;
+	mutex_lock(&epc->lock);
+	func_no = find_first_zero_bit(&epc->function_num_map,
+				      BITS_PER_LONG);
+	if (func_no >= BITS_PER_LONG) {
+		ret = -EINVAL;
+		goto ret;
+	}
+
+	if (func_no > epc->max_functions - 1) {
+		dev_err(&epc->dev, "Exceeding max supported Function Number\n");
+		ret = -EINVAL;
+		goto ret;
+	}
 
+	set_bit(func_no, &epc->function_num_map);
+	epf->func_no = func_no;
 	epf->epc = epc;
 
-	mutex_lock(&epc->lock);
 	list_add_tail(&epf->list, &epc->pci_epf);
+
+ret:
 	mutex_unlock(&epc->lock);
 
-	return 0;
+	return ret;
 }
 EXPORT_SYMBOL_GPL(pci_epc_add_epf);
 
@@ -503,6 +520,7 @@ void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf)
 		return;
 
 	mutex_lock(&epc->lock);
+	clear_bit(epf->func_no, &epc->function_num_map);
 	list_del(&epf->list);
 	epf->epc = NULL;
 	mutex_unlock(&epc->lock);
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 9b21692bc2e4..44bfbeb480bb 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -92,6 +92,7 @@ struct pci_epc_mem {
  * @max_functions: max number of functions that can be configured in this EPC
  * @group: configfs group representing the PCI EPC device
  * @lock: mutex to protect pci_epc ops
+ * @function_num_map: bitmap to manage physical function number
  * @notifier: used to notify EPF of any EPC events (like linkup)
  */
 struct pci_epc {
@@ -103,6 +104,7 @@ struct pci_epc {
 	struct config_group		*group;
 	/* mutex to protect against concurrent access of EP controller */
 	struct mutex			lock;
+	unsigned long			function_num_map;
 	struct atomic_notifier_head	notifier;
 };
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 27/50] PCI: endpoint: Add core init notifying feature
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (25 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 26/50] PCI: endpoint: Assign function number for each PF in EPC core Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion Lad Prabhakar
                   ` (24 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 906 bytes --]

From: Vidya Sagar <vidyas@nvidia.com>

commit 3d5f7d9f6a38ddcc105ebfb23b640630bbabba65 upstream.

Add a new feature core_init_notifier for cores that can notify about
their availability for initialization.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 include/linux/pci-epc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 44bfbeb480bb..8f9bbc4b7ad1 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -120,6 +120,7 @@ struct pci_epc {
  */
 struct pci_epc_features {
 	unsigned int	linkup_notifier : 1;
+	unsigned int	core_init_notifier : 1;
 	unsigned int	msi_capable : 1;
 	unsigned int	msix_capable : 1;
 	u8	reserved_bar;
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (26 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 27/50] PCI: endpoint: Add core init notifying feature Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-21 19:00   ` Pavel Machek
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 29/50] PCI: pci-epf-test: Add support to defer core initialization Lad Prabhakar
                   ` (23 subsequent siblings)
  51 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2608 bytes --]

From: Vidya Sagar <vidyas@nvidia.com>

commit 0ef22dcf0c1871888c4c0ee46a9d9c494f2fe997 upstream.

Add support to send notifications to EPF from EPC once the core
registers initialization is complete.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epc-core.c | 19 ++++++++++++++++++-
 include/linux/pci-epc.h             |  1 +
 include/linux/pci-epf.h             |  5 +++++
 3 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index dc1c673534e0..0d22a377a0cf 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -540,10 +540,27 @@ void pci_epc_linkup(struct pci_epc *epc)
 	if (!epc || IS_ERR(epc))
 		return;
 
-	atomic_notifier_call_chain(&epc->notifier, 0, NULL);
+	atomic_notifier_call_chain(&epc->notifier, LINK_UP, NULL);
 }
 EXPORT_SYMBOL_GPL(pci_epc_linkup);
 
+/**
+ * pci_epc_init_notify() - Notify the EPF device that EPC device's core
+ *			   initialization is completed.
+ * @epc: the EPC device whose core initialization is completeds
+ *
+ * Invoke to Notify the EPF device that the EPC device's initialization
+ * is completed.
+ */
+void pci_epc_init_notify(struct pci_epc *epc)
+{
+	if (!epc || IS_ERR(epc))
+		return;
+
+	atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL);
+}
+EXPORT_SYMBOL_GPL(pci_epc_init_notify);
+
 /**
  * pci_epc_destroy() - destroy the EPC device
  * @epc: the EPC device that has to be destroyed
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 8f9bbc4b7ad1..77e04ee1fe05 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -165,6 +165,7 @@ void devm_pci_epc_destroy(struct device *dev, struct pci_epc *epc);
 void pci_epc_destroy(struct pci_epc *epc);
 int pci_epc_add_epf(struct pci_epc *epc, struct pci_epf *epf);
 void pci_epc_linkup(struct pci_epc *epc);
+void pci_epc_init_notify(struct pci_epc *epc);
 void pci_epc_remove_epf(struct pci_epc *epc, struct pci_epf *epf);
 int pci_epc_write_header(struct pci_epc *epc, u8 func_no,
 			 struct pci_epf_header *hdr);
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index bcdf4f07bde7..0c628e30c582 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -15,6 +15,11 @@
 
 struct pci_epf;
 
+enum pci_notify_event {
+	CORE_INIT,
+	LINK_UP,
+};
+
 enum pci_barno {
 	BAR_0,
 	BAR_1,
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 29/50] PCI: pci-epf-test: Add support to defer core initialization
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (27 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 30/50] PCI: endpoint: Fix clearing start entry in configfs Lad Prabhakar
                   ` (22 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 5296 bytes --]

From: Vidya Sagar <vidyas@nvidia.com>

commit 5e50ee27d4a52a817ab152128c48690ec7c5cdf1 upstream.

Add support to defer core initialization for the endpoint mode of
operation.

This would enable support for implementations where the core
initialization needs to be deferred until the PCIe reference clock is
available from the host system.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 118 ++++++++++++------
 1 file changed, 77 insertions(+), 41 deletions(-)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 7dd40ab8b5d2..865a09d583df 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -360,18 +360,6 @@ static void pci_epf_test_cmd_handler(struct work_struct *work)
 			   msecs_to_jiffies(1));
 }
 
-static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
-				 void *data)
-{
-	struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
-	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
-
-	queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
-			   msecs_to_jiffies(1));
-
-	return NOTIFY_OK;
-}
-
 static void pci_epf_test_unbind(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
@@ -428,6 +416,78 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 	return 0;
 }
 
+static int pci_epf_test_core_init(struct pci_epf *epf)
+{
+	struct pci_epf_header *header = epf->header;
+	const struct pci_epc_features *epc_features;
+	struct pci_epc *epc = epf->epc;
+	struct device *dev = &epf->dev;
+	bool msix_capable = false;
+	bool msi_capable = true;
+	int ret;
+
+	epc_features = pci_epc_get_features(epc, epf->func_no);
+	if (epc_features) {
+		msix_capable = epc_features->msix_capable;
+		msi_capable = epc_features->msi_capable;
+	}
+
+	ret = pci_epc_write_header(epc, epf->func_no, header);
+	if (ret) {
+		dev_err(dev, "Configuration header write failed\n");
+		return ret;
+	}
+
+	ret = pci_epf_test_set_bar(epf);
+	if (ret)
+		return ret;
+
+	if (msi_capable) {
+		ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
+		if (ret) {
+			dev_err(dev, "MSI configuration failed\n");
+			return ret;
+		}
+	}
+
+	if (msix_capable) {
+		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
+		if (ret) {
+			dev_err(dev, "MSI-X configuration failed\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val,
+				 void *data)
+{
+	struct pci_epf *epf = container_of(nb, struct pci_epf, nb);
+	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
+	int ret;
+
+	switch (val) {
+	case CORE_INIT:
+		ret = pci_epf_test_core_init(epf);
+		if (ret)
+			return NOTIFY_BAD;
+		break;
+
+	case LINK_UP:
+		queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler,
+				   msecs_to_jiffies(1));
+		break;
+
+	default:
+		dev_err(&epf->dev, "Invalid EPF test notifier event\n");
+		return NOTIFY_BAD;
+	}
+
+	return NOTIFY_OK;
+}
+
 static int pci_epf_test_alloc_space(struct pci_epf *epf)
 {
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
@@ -496,14 +556,11 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 {
 	int ret;
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
-	struct pci_epf_header *header = epf->header;
 	const struct pci_epc_features *epc_features;
 	enum pci_barno test_reg_bar = BAR_0;
 	struct pci_epc *epc = epf->epc;
-	struct device *dev = &epf->dev;
 	bool linkup_notifier = false;
-	bool msix_capable = false;
-	bool msi_capable = true;
+	bool core_init_notifier = false;
 
 	if (WARN_ON_ONCE(!epc))
 		return -EINVAL;
@@ -511,8 +568,7 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	epc_features = pci_epc_get_features(epc, epf->func_no);
 	if (epc_features) {
 		linkup_notifier = epc_features->linkup_notifier;
-		msix_capable = epc_features->msix_capable;
-		msi_capable = epc_features->msi_capable;
+		core_init_notifier = epc_features->core_init_notifier;
 		test_reg_bar = pci_epc_get_first_free_bar(epc_features);
 		pci_epf_configure_bar(epf, epc_features);
 	}
@@ -520,34 +576,14 @@ static int pci_epf_test_bind(struct pci_epf *epf)
 	epf_test->test_reg_bar = test_reg_bar;
 	epf_test->epc_features = epc_features;
 
-	ret = pci_epc_write_header(epc, epf->func_no, header);
-	if (ret) {
-		dev_err(dev, "Configuration header write failed\n");
-		return ret;
-	}
-
 	ret = pci_epf_test_alloc_space(epf);
 	if (ret)
 		return ret;
 
-	ret = pci_epf_test_set_bar(epf);
-	if (ret)
-		return ret;
-
-	if (msi_capable) {
-		ret = pci_epc_set_msi(epc, epf->func_no, epf->msi_interrupts);
-		if (ret) {
-			dev_err(dev, "MSI configuration failed\n");
-			return ret;
-		}
-	}
-
-	if (msix_capable) {
-		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
-		if (ret) {
-			dev_err(dev, "MSI-X configuration failed\n");
+	if (!core_init_notifier) {
+		ret = pci_epf_test_core_init(epf);
+		if (ret)
 			return ret;
-		}
 	}
 
 	if (linkup_notifier) {
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 30/50] PCI: endpoint: Fix clearing start entry in configfs
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (28 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 29/50] PCI: pci-epf-test: Add support to defer core initialization Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 31/50] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Lad Prabhakar
                   ` (21 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1365 bytes --]

From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>

commit f58d5f53c89479c12ad719c1960176442add5aaa upstream.

After an endpoint is started through configfs, if 0 is written to the
configfs entry 'start', the controller stops but the epc_group->start
value remains 1.

A subsequent unlinking of the function from the controller would trigger
a spurious WARN_ON_ONCE() in pci_epc_epf_unlink() despite right
behavior.

Fix it by setting epc_group->start = 0 when a controller is stopped
using configfs.

Fixes: d74679911610 ("PCI: endpoint: Introduce configfs entry for configuring EP functions")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-ep-cfs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c
index e7e8367eead1..55edce50be96 100644
--- a/drivers/pci/endpoint/pci-ep-cfs.c
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -57,6 +57,7 @@ static ssize_t pci_epc_start_store(struct config_item *item, const char *page,
 
 	if (!start) {
 		pci_epc_stop(epc);
+		epc_group->start = 0;
 		return len;
 	}
 
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 31/50] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (29 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 30/50] PCI: endpoint: Fix clearing start entry in configfs Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 32/50] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address Lad Prabhakar
                   ` (20 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 7650 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 83153d9f36e24978c6211d246cb6f532bf54e5dc upstream.

commit 8963106eabdc ("PCI: endpoint: Add MSI-X interfaces") while
adding support to raise MSI-X interrupts from endpoint didn't include
BAR Indicator register (BIR) configuration and MSI-X table offset as
arguments in pci_epc_set_msix(). This would result in endpoint
controller register using random BAR indicator register, the memory
for which might not be allocated by the endpoint function driver.
Add BAR indicator register and MSI-X table offset as arguments in
pci_epc_set_msix() and allocate space for MSI-X table and pending
bit array (PBA) in pci-epf-test endpoint function driver.

Fixes: 8963106eabdc ("PCI: endpoint: Add MSI-X interfaces")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../pci/controller/dwc/pcie-designware-ep.c   | 15 +++++++--
 drivers/pci/endpoint/functions/pci-epf-test.c | 32 +++++++++++++++----
 drivers/pci/endpoint/pci-epc-core.c           |  7 ++--
 include/linux/pci-epc.h                       |  6 ++--
 4 files changed, 48 insertions(+), 12 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index d1bb4b852b6c..667763fd868f 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -302,7 +302,8 @@ static int dw_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
 	return val;
 }
 
-static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
+static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
+			       enum pci_barno bir, u32 offset)
 {
 	struct dw_pcie_ep *ep = epc_get_drvdata(epc);
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -311,12 +312,22 @@ static int dw_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
 	if (!ep->msix_cap)
 		return -EINVAL;
 
+	dw_pcie_dbi_ro_wr_en(pci);
+
 	reg = ep->msix_cap + PCI_MSIX_FLAGS;
 	val = dw_pcie_readw_dbi(pci, reg);
 	val &= ~PCI_MSIX_FLAGS_QSIZE;
 	val |= interrupts;
-	dw_pcie_dbi_ro_wr_en(pci);
 	dw_pcie_writew_dbi(pci, reg, val);
+
+	reg = ep->msix_cap + PCI_MSIX_TABLE;
+	val = offset | bir;
+	dw_pcie_writel_dbi(pci, reg, val);
+
+	reg = ep->msix_cap + PCI_MSIX_PBA;
+	val = (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir;
+	dw_pcie_writel_dbi(pci, reg, val);
+
 	dw_pcie_dbi_ro_wr_dis(pci);
 
 	return 0;
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 865a09d583df..f6905c242194 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -47,6 +47,7 @@ struct pci_epf_test {
 	void			*reg[6];
 	struct pci_epf		*epf;
 	enum pci_barno		test_reg_bar;
+	size_t			msix_table_offset;
 	struct delayed_work	cmd_handler;
 	const struct pci_epc_features *epc_features;
 };
@@ -418,6 +419,7 @@ static int pci_epf_test_set_bar(struct pci_epf *epf)
 
 static int pci_epf_test_core_init(struct pci_epf *epf)
 {
+	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 	struct pci_epf_header *header = epf->header;
 	const struct pci_epc_features *epc_features;
 	struct pci_epc *epc = epf->epc;
@@ -451,7 +453,9 @@ static int pci_epf_test_core_init(struct pci_epf *epf)
 	}
 
 	if (msix_capable) {
-		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts);
+		ret = pci_epc_set_msix(epc, epf->func_no, epf->msix_interrupts,
+				       epf_test->test_reg_bar,
+				       epf_test->msix_table_offset);
 		if (ret) {
 			dev_err(dev, "MSI-X configuration failed\n");
 			return ret;
@@ -493,6 +497,10 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 	struct pci_epf_test *epf_test = epf_get_drvdata(epf);
 	struct device *dev = &epf->dev;
 	struct pci_epf_bar *epf_bar;
+	size_t msix_table_size = 0;
+	size_t test_reg_bar_size;
+	size_t pba_size = 0;
+	bool msix_capable;
 	void *base;
 	int bar, add;
 	enum pci_barno test_reg_bar = epf_test->test_reg_bar;
@@ -501,13 +509,25 @@ static int pci_epf_test_alloc_space(struct pci_epf *epf)
 
 	epc_features = epf_test->epc_features;
 
-	if (epc_features->bar_fixed_size[test_reg_bar])
+	test_reg_bar_size = ALIGN(sizeof(struct pci_epf_test_reg), 128);
+
+	msix_capable = epc_features->msix_capable;
+	if (msix_capable) {
+		msix_table_size = PCI_MSIX_ENTRY_SIZE * epf->msix_interrupts;
+		epf_test->msix_table_offset = test_reg_bar_size;
+		/* Align to QWORD or 8 Bytes */
+		pba_size = ALIGN(DIV_ROUND_UP(epf->msix_interrupts, 8), 8);
+	}
+	test_reg_size = test_reg_bar_size + msix_table_size + pba_size;
+
+	if (epc_features->bar_fixed_size[test_reg_bar]) {
+		if (test_reg_size > bar_size[test_reg_bar])
+			return -ENOMEM;
 		test_reg_size = bar_size[test_reg_bar];
-	else
-		test_reg_size = sizeof(struct pci_epf_test_reg);
+	}
 
-	base = pci_epf_alloc_space(epf, test_reg_size,
-				   test_reg_bar, epc_features->align);
+	base = pci_epf_alloc_space(epf, test_reg_size, test_reg_bar,
+				   epc_features->align);
 	if (!base) {
 		dev_err(dev, "Failed to allocated register space\n");
 		return -ENOMEM;
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 0d22a377a0cf..82ba0dc7f2f5 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -297,10 +297,13 @@ EXPORT_SYMBOL_GPL(pci_epc_get_msix);
  * @epc: the EPC device on which MSI-X has to be configured
  * @func_no: the endpoint function number in the EPC device
  * @interrupts: number of MSI-X interrupts required by the EPF
+ * @bir: BAR where the MSI-X table resides
+ * @offset: Offset pointing to the start of MSI-X table
  *
  * Invoke to set the required number of MSI-X interrupts.
  */
-int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
+int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
+		     enum pci_barno bir, u32 offset)
 {
 	int ret;
 
@@ -312,7 +315,7 @@ int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts)
 		return 0;
 
 	mutex_lock(&epc->lock);
-	ret = epc->ops->set_msix(epc, func_no, interrupts - 1);
+	ret = epc->ops->set_msix(epc, func_no, interrupts - 1, bir, offset);
 	mutex_unlock(&epc->lock);
 
 	return ret;
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 77e04ee1fe05..8c86841fcdaf 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -53,7 +53,8 @@ struct pci_epc_ops {
 			      phys_addr_t addr);
 	int	(*set_msi)(struct pci_epc *epc, u8 func_no, u8 interrupts);
 	int	(*get_msi)(struct pci_epc *epc, u8 func_no);
-	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts);
+	int	(*set_msix)(struct pci_epc *epc, u8 func_no, u16 interrupts,
+			    enum pci_barno, u32 offset);
 	int	(*get_msix)(struct pci_epc *epc, u8 func_no);
 	int	(*raise_irq)(struct pci_epc *epc, u8 func_no,
 			     enum pci_epc_irq_type type, u16 interrupt_num);
@@ -180,7 +181,8 @@ void pci_epc_unmap_addr(struct pci_epc *epc, u8 func_no,
 			phys_addr_t phys_addr);
 int pci_epc_set_msi(struct pci_epc *epc, u8 func_no, u8 interrupts);
 int pci_epc_get_msi(struct pci_epc *epc, u8 func_no);
-int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts);
+int pci_epc_set_msix(struct pci_epc *epc, u8 func_no, u16 interrupts,
+		     enum pci_barno, u32 offset);
 int pci_epc_get_msix(struct pci_epc *epc, u8 func_no);
 int pci_epc_raise_irq(struct pci_epc *epc, u8 func_no,
 		      enum pci_epc_irq_type type, u16 interrupt_num);
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 32/50] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (30 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 31/50] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 33/50] PCI: endpoint: Pass page size as argument to pci_epc_mem_init() Lad Prabhakar
                   ` (19 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2926 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 6f5e193bfb55963ce5f4f68cc927f371ddb0913b upstream.

commit beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler"),
in order to raise MSI-X interrupt, obtained MSIX table address from
Base Address Register (BAR). However BAR only holds PCI address
programmed by the host whereas the MSI-X table should be in the local
memory.

Store the MSI-X table address (virtual address) as part of ->set_bar()
callback and use that to get the message address and message data
here.

Fixes: beb4641a787d ("PCI: dwc: Add MSI-X callbacks handler")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
[PL: Dropppped changes to designware driver]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/pci-epf-core.c |  2 ++
 include/linux/pci-epf.h             | 15 +++++++++++++++
 2 files changed, 17 insertions(+)

diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c
index 6e0648991b5c..244e00f48c5c 100644
--- a/drivers/pci/endpoint/pci-epf-core.c
+++ b/drivers/pci/endpoint/pci-epf-core.c
@@ -87,6 +87,7 @@ void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar)
 			  epf->bar[bar].phys_addr);
 
 	epf->bar[bar].phys_addr = 0;
+	epf->bar[bar].addr = NULL;
 	epf->bar[bar].size = 0;
 	epf->bar[bar].barno = 0;
 	epf->bar[bar].flags = 0;
@@ -123,6 +124,7 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar,
 	}
 
 	epf->bar[bar].phys_addr = phys_addr;
+	epf->bar[bar].addr = space;
 	epf->bar[bar].size = size;
 	epf->bar[bar].barno = bar;
 	epf->bar[bar].flags |= upper_32_bits(size) ?
diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h
index 0c628e30c582..6644ff3b0702 100644
--- a/include/linux/pci-epf.h
+++ b/include/linux/pci-epf.h
@@ -94,10 +94,12 @@ struct pci_epf_driver {
 /**
  * struct pci_epf_bar - represents the BAR of EPF device
  * @phys_addr: physical address that should be mapped to the BAR
+ * @addr: virtual address corresponding to the @phys_addr
  * @size: the size of the address space present in BAR
  */
 struct pci_epf_bar {
 	dma_addr_t	phys_addr;
+	void		*addr;
 	size_t		size;
 	enum pci_barno	barno;
 	int		flags;
@@ -134,6 +136,19 @@ struct pci_epf {
 	struct mutex		lock;
 };
 
+/**
+ * struct pci_epf_msix_tbl - represents the MSIX table entry structure
+ * @msg_addr: Writes to this address will trigger MSIX interrupt in host
+ * @msg_data: Data that should be written to @msg_addr to trigger MSIX interrupt
+ * @vector_ctrl: Identifies if the function is prohibited from sending a message
+ * using this MSIX table entry
+ */
+struct pci_epf_msix_tbl {
+	u64 msg_addr;
+	u32 msg_data;
+	u32 vector_ctrl;
+};
+
 #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev)
 
 #define pci_epf_register_driver(driver)    \
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 33/50] PCI: endpoint: Pass page size as argument to pci_epc_mem_init()
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (31 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 32/50] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 34/50] PCI: endpoint: Add support to handle multiple base for mapping outbound memory Lad Prabhakar
                   ` (18 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 3937 bytes --]

commit 975cf23e3aa89588cbfc9ad6f2b23bd32af4edc7 upstream.

pci_epc_mem_init() internally used page size equal to *PAGE_SIZE* to
manage the address space so instead just pass the page size as a
argument to pci_epc_mem_init().

Also make pci_epc_mem_init() as a C function instead of a macro function
in preparation for adding support for pci-epc-mem core to handle multiple
windows.

Link: https://lore.kernel.org/r/1588854799-13710-5-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
[PL: Manually applied changes to pcie-cadence-ep.c]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-cadence-ep.c  | 2 +-
 drivers/pci/controller/pcie-rockchip-ep.c | 2 +-
 drivers/pci/endpoint/pci-epc-mem.c        | 7 +++++++
 include/linux/pci-epc.h                   | 5 ++---
 4 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c
index def7820cb824..3575c8e3e398 100644
--- a/drivers/pci/controller/pcie-cadence-ep.c
+++ b/drivers/pci/controller/pcie-cadence-ep.c
@@ -503,7 +503,7 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev)
 		epc->max_functions = 1;
 
 	ret = pci_epc_mem_init(epc, pcie->mem_res->start,
-			       resource_size(pcie->mem_res));
+			       resource_size(pcie->mem_res), PAGE_SIZE);
 	if (ret < 0) {
 		dev_err(dev, "failed to initialize the memory space\n");
 		goto err_init;
diff --git a/drivers/pci/controller/pcie-rockchip-ep.c b/drivers/pci/controller/pcie-rockchip-ep.c
index d743b0a48988..5eaf36629a75 100644
--- a/drivers/pci/controller/pcie-rockchip-ep.c
+++ b/drivers/pci/controller/pcie-rockchip-ep.c
@@ -615,7 +615,7 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
 	rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
 
 	err = pci_epc_mem_init(epc, rockchip->mem_res->start,
-			       resource_size(rockchip->mem_res));
+			       resource_size(rockchip->mem_res), PAGE_SIZE);
 	if (err < 0) {
 		dev_err(dev, "failed to initialize the memory space\n");
 		goto err_uninit_port;
diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c
index abfac1109a13..cdd1d3821249 100644
--- a/drivers/pci/endpoint/pci-epc-mem.c
+++ b/drivers/pci/endpoint/pci-epc-mem.c
@@ -93,6 +93,13 @@ return ret;
 }
 EXPORT_SYMBOL_GPL(__pci_epc_mem_init);
 
+int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
+		     size_t size, size_t page_size)
+{
+	return __pci_epc_mem_init(epc, base, size, page_size);
+}
+EXPORT_SYMBOL_GPL(pci_epc_mem_init);
+
 /**
  * pci_epc_mem_exit() - cleanup the pci_epc_mem structure
  * @epc: the EPC device that invoked pci_epc_mem_exit
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index 8c86841fcdaf..e5f6ca8c36a8 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -137,9 +137,6 @@ struct pci_epc_features {
 #define devm_pci_epc_create(dev, ops)    \
 		__devm_pci_epc_create((dev), (ops), THIS_MODULE)
 
-#define pci_epc_mem_init(epc, phys_addr, size)	\
-		__pci_epc_mem_init((epc), (phys_addr), (size), PAGE_SIZE)
-
 static inline void epc_set_drvdata(struct pci_epc *epc, void *data)
 {
 	dev_set_drvdata(&epc->dev, data);
@@ -195,6 +192,8 @@ unsigned int pci_epc_get_first_free_bar(const struct pci_epc_features
 struct pci_epc *pci_epc_get(const char *epc_name);
 void pci_epc_put(struct pci_epc *epc);
 
+int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
+		     size_t size, size_t page_size);
 int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
 		       size_t page_size);
 void pci_epc_mem_exit(struct pci_epc *epc);
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 34/50] PCI: endpoint: Add support to handle multiple base for mapping outbound memory
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (32 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 33/50] PCI: endpoint: Pass page size as argument to pci_epc_mem_init() Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 35/50] PCI: endpoint: functions/pci-epf-test: Print throughput information Lad Prabhakar
                   ` (17 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 13491 bytes --]

commit d45e3c1a5979efd40dbbac9a5c3586f4fa41f734 upstream.

R-Car PCIe controller has support to map multiple memory regions for
mapping the outbound memory in local system also the controller limits
single allocation for each region (that is, once a chunk is used from the
region it cannot be used to allocate a new one). This features inspires to
add support for handling multiple memory bases in endpoint framework.

With this patch pci_epc_mem_init() initializes address space for endpoint
controller which support single window and pci_epc_multi_mem_init()
initializes multiple windows supported by endpoint controller.

Link: https://lore.kernel.org/r/1588854799-13710-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
[PL: manually applied changes to pcie-designware-ep.c]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../pci/controller/dwc/pcie-designware-ep.c   |  12 +-
 drivers/pci/endpoint/pci-epc-mem.c            | 199 ++++++++++++------
 include/linux/pci-epc.h                       |  33 ++-
 3 files changed, 168 insertions(+), 76 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 667763fd868f..471855feab03 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -434,11 +434,11 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
 		reg = ep->msi_cap + PCI_MSI_DATA_32;
 		msg_data = dw_pcie_readw_dbi(pci, reg);
 	}
-	aligned_offset = msg_addr_lower & (epc->mem->page_size - 1);
+	aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1);
 	msg_addr = ((u64)msg_addr_upper) << 32 |
 			(msg_addr_lower & ~aligned_offset);
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
-				  epc->mem->page_size);
+				  epc->mem->window.page_size);
 	if (ret)
 		return ret;
 
@@ -495,7 +495,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 		return -EPERM;
 
 	ret = dw_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys, msg_addr,
-				  epc->mem->page_size);
+				  epc->mem->window.page_size);
 	if (ret)
 		return ret;
 
@@ -511,7 +511,7 @@ void dw_pcie_ep_exit(struct dw_pcie_ep *ep)
 	struct pci_epc *epc = ep->epc;
 
 	pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
-			      epc->mem->page_size);
+			      epc->mem->window.page_size);
 
 	pci_epc_mem_exit(epc);
 }
@@ -586,7 +586,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	if (ret < 0)
 		epc->max_functions = 1;
 
-	ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
+	ret = pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
 				 ep->page_size);
 	if (ret < 0) {
 		dev_err(dev, "Failed to initialize address space\n");
@@ -594,7 +594,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
 	}
 
 	ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
-					     epc->mem->page_size);
+					     epc->mem->window.page_size);
 	if (!ep->msi_mem) {
 		dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
 		return -ENOMEM;
diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c
index cdd1d3821249..80c46f3a4590 100644
--- a/drivers/pci/endpoint/pci-epc-mem.c
+++ b/drivers/pci/endpoint/pci-epc-mem.c
@@ -23,7 +23,7 @@
 static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size)
 {
 	int order;
-	unsigned int page_shift = ilog2(mem->page_size);
+	unsigned int page_shift = ilog2(mem->window.page_size);
 
 	size--;
 	size >>= page_shift;
@@ -36,67 +36,95 @@ static int pci_epc_mem_get_order(struct pci_epc_mem *mem, size_t size)
 }
 
 /**
- * __pci_epc_mem_init() - initialize the pci_epc_mem structure
+ * pci_epc_multi_mem_init() - initialize the pci_epc_mem structure
  * @epc: the EPC device that invoked pci_epc_mem_init
- * @phys_base: the physical address of the base
- * @size: the size of the address space
- * @page_size: size of each page
+ * @windows: pointer to windows supported by the device
+ * @num_windows: number of windows device supports
  *
  * Invoke to initialize the pci_epc_mem structure used by the
  * endpoint functions to allocate mapped PCI address.
  */
-int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_base, size_t size,
-		       size_t page_size)
+int pci_epc_multi_mem_init(struct pci_epc *epc,
+			   struct pci_epc_mem_window *windows,
+			   unsigned int num_windows)
 {
-	int ret;
-	struct pci_epc_mem *mem;
-	unsigned long *bitmap;
+	struct pci_epc_mem *mem = NULL;
+	unsigned long *bitmap = NULL;
 	unsigned int page_shift;
-	int pages;
+	size_t page_size;
 	int bitmap_size;
+	int pages;
+	int ret;
+	int i;
 
-	if (page_size < PAGE_SIZE)
-		page_size = PAGE_SIZE;
+	epc->num_windows = 0;
 
-	page_shift = ilog2(page_size);
-	pages = size >> page_shift;
-	bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
+	if (!windows || !num_windows)
+		return -EINVAL;
 
-	mem = kzalloc(sizeof(*mem), GFP_KERNEL);
-	if (!mem) {
-		ret = -ENOMEM;
-		goto err;
-	}
+	epc->windows = kcalloc(num_windows, sizeof(*epc->windows), GFP_KERNEL);
+	if (!epc->windows)
+		return -ENOMEM;
 
-	bitmap = kzalloc(bitmap_size, GFP_KERNEL);
-	if (!bitmap) {
-		ret = -ENOMEM;
-		goto err_mem;
-	}
+	for (i = 0; i < num_windows; i++) {
+		page_size = windows[i].page_size;
+		if (page_size < PAGE_SIZE)
+			page_size = PAGE_SIZE;
+		page_shift = ilog2(page_size);
+		pages = windows[i].size >> page_shift;
+		bitmap_size = BITS_TO_LONGS(pages) * sizeof(long);
 
-	mem->bitmap = bitmap;
-	mem->phys_base = phys_base;
-	mem->page_size = page_size;
-	mem->pages = pages;
-	mem->size = size;
-	mutex_init(&mem->lock);
+		mem = kzalloc(sizeof(*mem), GFP_KERNEL);
+		if (!mem) {
+			ret = -ENOMEM;
+			i--;
+			goto err_mem;
+		}
 
-	epc->mem = mem;
+		bitmap = kzalloc(bitmap_size, GFP_KERNEL);
+		if (!bitmap) {
+			ret = -ENOMEM;
+			kfree(mem);
+			i--;
+			goto err_mem;
+		}
+
+		mem->window.phys_base = windows[i].phys_base;
+		mem->window.size = windows[i].size;
+		mem->window.page_size = page_size;
+		mem->bitmap = bitmap;
+		mem->pages = pages;
+		mutex_init(&mem->lock);
+		epc->windows[i] = mem;
+	}
+
+	epc->mem = epc->windows[0];
+	epc->num_windows = num_windows;
 
 	return 0;
 
 err_mem:
-	kfree(mem);
+	for (; i >= 0; i--) {
+		mem = epc->windows[i];
+		kfree(mem->bitmap);
+		kfree(mem);
+	}
+	kfree(epc->windows);
 
-err:
-return ret;
+	return ret;
 }
-EXPORT_SYMBOL_GPL(__pci_epc_mem_init);
+EXPORT_SYMBOL_GPL(pci_epc_multi_mem_init);
 
 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
 		     size_t size, size_t page_size)
 {
-	return __pci_epc_mem_init(epc, base, size, page_size);
+	struct pci_epc_mem_window mem_window;
+
+	mem_window.phys_base = base;
+	mem_window.size = size;
+	mem_window.page_size = page_size;
+
+	return pci_epc_multi_mem_init(epc, &mem_window, 1);
 }
 EXPORT_SYMBOL_GPL(pci_epc_mem_init);
 
@@ -109,11 +137,22 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_init);
  */
 void pci_epc_mem_exit(struct pci_epc *epc)
 {
-	struct pci_epc_mem *mem = epc->mem;
+	struct pci_epc_mem *mem;
+	int i;
 
+	if (!epc->num_windows)
+		return;
+
+	for (i = 0; i < epc->num_windows; i++) {
+		mem = epc->windows[i];
+		kfree(mem->bitmap);
+		kfree(mem);
+	}
+	kfree(epc->windows);
+
+	epc->windows = NULL;
 	epc->mem = NULL;
-	kfree(mem->bitmap);
-	kfree(mem);
+	epc->num_windows = 0;
 }
 EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
 
@@ -129,31 +168,60 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_exit);
 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
 				     phys_addr_t *phys_addr, size_t size)
 {
-	int pageno;
 	void __iomem *virt_addr = NULL;
-	struct pci_epc_mem *mem = epc->mem;
-	unsigned int page_shift = ilog2(mem->page_size);
+	struct pci_epc_mem *mem;
+	unsigned int page_shift;
+	size_t align_size;
+	int pageno;
 	int order;
+	int i;
 
-	size = ALIGN(size, mem->page_size);
-	order = pci_epc_mem_get_order(mem, size);
-
-	mutex_lock(&mem->lock);
-	pageno = bitmap_find_free_region(mem->bitmap, mem->pages, order);
-	if (pageno < 0)
-		goto ret;
+	for (i = 0; i < epc->num_windows; i++) {
+		mem = epc->windows[i];
+		mutex_lock(&mem->lock);
+		align_size = ALIGN(size, mem->window.page_size);
+		order = pci_epc_mem_get_order(mem, align_size);
 
-	*phys_addr = mem->phys_base + ((phys_addr_t)pageno << page_shift);
-	virt_addr = ioremap(*phys_addr, size);
-	if (!virt_addr)
-		bitmap_release_region(mem->bitmap, pageno, order);
+		pageno = bitmap_find_free_region(mem->bitmap, mem->pages,
+						 order);
+		if (pageno >= 0) {
+			page_shift = ilog2(mem->window.page_size);
+			*phys_addr = mem->window.phys_base +
+				((phys_addr_t)pageno << page_shift);
+			virt_addr = ioremap(*phys_addr, align_size);
+			if (!virt_addr) {
+				bitmap_release_region(mem->bitmap,
+						      pageno, order);
+				mutex_unlock(&mem->lock);
+				continue;
+			}
+			mutex_unlock(&mem->lock);
+			return virt_addr;
+		}
+		mutex_unlock(&mem->lock);
+	}
 
-ret:
-	mutex_unlock(&mem->lock);
 	return virt_addr;
 }
 EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
 
+static struct pci_epc_mem *pci_epc_get_matching_window(struct pci_epc *epc,
+						       phys_addr_t phys_addr)
+{
+	struct pci_epc_mem *mem;
+	int i;
+
+	for (i = 0; i < epc->num_windows; i++) {
+		mem = epc->windows[i];
+
+		if (phys_addr >= mem->window.phys_base &&
+		    phys_addr < (mem->window.phys_base + mem->window.size))
+			return mem;
+	}
+
+	return NULL;
+}
+
 /**
  * pci_epc_mem_free_addr() - free the allocated memory address
  * @epc: the EPC device on which memory was allocated
@@ -166,14 +234,23 @@ EXPORT_SYMBOL_GPL(pci_epc_mem_alloc_addr);
 void pci_epc_mem_free_addr(struct pci_epc *epc, phys_addr_t phys_addr,
 			   void __iomem *virt_addr, size_t size)
 {
+	struct pci_epc_mem *mem;
+	unsigned int page_shift;
+	size_t page_size;
 	int pageno;
-	struct pci_epc_mem *mem = epc->mem;
-	unsigned int page_shift = ilog2(mem->page_size);
 	int order;
 
+	mem = pci_epc_get_matching_window(epc, phys_addr);
+	if (!mem) {
+		pr_err("failed to get matching window\n");
+		return;
+	}
+
+	page_size = mem->window.page_size;
+	page_shift = ilog2(page_size);
 	iounmap(virt_addr);
-	pageno = (phys_addr - mem->phys_base) >> page_shift;
-	size = ALIGN(size, mem->page_size);
+	pageno = (phys_addr - mem->window.phys_base) >> page_shift;
+	size = ALIGN(size, page_size);
 	order = pci_epc_mem_get_order(mem, size);
 	mutex_lock(&mem->lock);
 	bitmap_release_region(mem->bitmap, pageno, order);
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index e5f6ca8c36a8..5adb881bbcd7 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -65,20 +65,28 @@ struct pci_epc_ops {
 	struct module *owner;
 };
 
+/**
+ * struct pci_epc_mem_window - address window of the endpoint controller
+ * @phys_base: physical base address of the PCI address window
+ * @size: the size of the PCI address window
+ * @page_size: size of each page
+ */
+struct pci_epc_mem_window {
+	phys_addr_t	phys_base;
+	size_t		size;
+	size_t		page_size;
+};
+
 /**
  * struct pci_epc_mem - address space of the endpoint controller
- * @phys_base: physical base address of the PCI address space
- * @size: the size of the PCI address space
+ * @window: address window of the endpoint controller
  * @bitmap: bitmap to manage the PCI address space
  * @pages: number of bits representing the address region
- * @page_size: size of each page
  * @lock: mutex to protect bitmap
  */
 struct pci_epc_mem {
-	phys_addr_t	phys_base;
-	size_t		size;
+	struct pci_epc_mem_window window;
 	unsigned long	*bitmap;
-	size_t		page_size;
 	int		pages;
 	/* mutex to protect against concurrent access for memory allocation*/
 	struct mutex	lock;
@@ -89,7 +97,11 @@ struct pci_epc_mem {
  * @dev: PCI EPC device
  * @pci_epf: list of endpoint functions present in this EPC device
  * @ops: function pointers for performing endpoint operations
- * @mem: address space of the endpoint controller
+ * @windows: array of address space of the endpoint controller
+ * @mem: first window of the endpoint controller, which corresponds to
+ *       default address space of the endpoint controller supporting
+ *       single window.
+ * @num_windows: number of windows supported by device
  * @max_functions: max number of functions that can be configured in this EPC
  * @group: configfs group representing the PCI EPC device
  * @lock: mutex to protect pci_epc ops
@@ -100,7 +112,9 @@ struct pci_epc {
 	struct device			dev;
 	struct list_head		pci_epf;
 	const struct pci_epc_ops	*ops;
+	struct pci_epc_mem		**windows;
 	struct pci_epc_mem		*mem;
+	unsigned int			num_windows;
 	u8				max_functions;
 	struct config_group		*group;
 	/* mutex to protect against concurrent access of EP controller */
@@ -194,8 +208,9 @@ void pci_epc_put(struct pci_epc *epc);
 
 int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base,
 		     size_t size, size_t page_size);
-int __pci_epc_mem_init(struct pci_epc *epc, phys_addr_t phys_addr, size_t size,
-		       size_t page_size);
+int pci_epc_multi_mem_init(struct pci_epc *epc,
+			   struct pci_epc_mem_window *window,
+			   unsigned int num_windows);
 void pci_epc_mem_exit(struct pci_epc *epc);
 void __iomem *pci_epc_mem_alloc_addr(struct pci_epc *epc,
 				     phys_addr_t *phys_addr, size_t size);
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 35/50] PCI: endpoint: functions/pci-epf-test: Print throughput information
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (33 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 34/50] PCI: endpoint: Add support to handle multiple base for mapping outbound memory Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 36/50] PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c Lad Prabhakar
                   ` (16 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 3909 bytes --]

From: Kishon Vijay Abraham I <kishon@ti.com>

commit 5893c2e5353bb9a723d862d8b6ba8028a8f6a6eb upstream.

Print throughput information in KB/s after every completed transfer,
including information on whether DMA is used or not.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Alan Mikhak <alan.mikhak@sifive.com>
[PL: Applied changes to pci-epf-test.c manually, always pass dma variable
to pci_epf_test_print_rate() function as false since streaming DMA support
is missing in EPF]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 44 +++++++++++++++++++
 1 file changed, 44 insertions(+)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index f6905c242194..8d9b5521ed50 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -73,6 +73,36 @@ static struct pci_epf_header test_header = {
 
 static size_t bar_size[] = { 512, 512, 1024, 16384, 131072, 1048576 };
 
+static void pci_epf_test_print_rate(const char *ops, u64 size,
+				    struct timespec64 *start,
+				    struct timespec64 *end, bool dma)
+{
+	struct timespec64 ts;
+	u64 rate, ns;
+
+	ts = timespec64_sub(*end, *start);
+
+	/* convert both size (stored in 'rate') and time in terms of 'ns' */
+	ns = timespec64_to_ns(&ts);
+	rate = size * NSEC_PER_SEC;
+
+	/* Divide both size (stored in 'rate') and ns by a common factor */
+	while (ns > UINT_MAX) {
+		rate >>= 1;
+		ns >>= 1;
+	}
+
+	if (!ns)
+		return;
+
+	/* calculate the rate */
+	do_div(rate, (uint32_t)ns);
+
+	pr_info("\n%s => Size: %llu bytes\t DMA: %s\t Time: %llu.%09u seconds\t"
+		"Rate: %llu KB/s\n", ops, size, dma ? "YES" : "NO",
+		(u64)ts.tv_sec, (u32)ts.tv_nsec, rate / 1024);
+}
+
 static int pci_epf_test_copy(struct pci_epf_test *epf_test)
 {
 	int ret;
@@ -80,6 +110,7 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
 	void __iomem *dst_addr;
 	phys_addr_t src_phys_addr;
 	phys_addr_t dst_phys_addr;
+	struct timespec64 start, end;
 	struct pci_epf *epf = epf_test->epf;
 	struct device *dev = &epf->dev;
 	struct pci_epc *epc = epf->epc;
@@ -118,7 +149,10 @@ static int pci_epf_test_copy(struct pci_epf_test *epf_test)
 		goto err_dst_addr;
 	}
 
+	ktime_get_ts64(&start);
 	memcpy(dst_addr, src_addr, reg->size);
+	ktime_get_ts64(&end);
+	pci_epf_test_print_rate("COPY", reg->size, &start, &end, false);
 
 	pci_epc_unmap_addr(epc, epf->func_no, dst_phys_addr);
 
@@ -142,6 +176,7 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
 	void *buf;
 	u32 crc32;
 	phys_addr_t phys_addr;
+	struct timespec64 start, end;
 	struct pci_epf *epf = epf_test->epf;
 	struct device *dev = &epf->dev;
 	struct pci_epc *epc = epf->epc;
@@ -170,7 +205,11 @@ static int pci_epf_test_read(struct pci_epf_test *epf_test)
 		goto err_map_addr;
 	}
 
+	ktime_get_ts64(&start);
 	memcpy_fromio(buf, src_addr, reg->size);
+	ktime_get_ts64(&end);
+
+	pci_epf_test_print_rate("READ", reg->size, &start, &end, false);
 
 	crc32 = crc32_le(~0, buf, reg->size);
 	if (crc32 != reg->checksum)
@@ -194,6 +233,7 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
 	void __iomem *dst_addr;
 	void *buf;
 	phys_addr_t phys_addr;
+	struct timespec64 start, end;
 	struct pci_epf *epf = epf_test->epf;
 	struct device *dev = &epf->dev;
 	struct pci_epc *epc = epf->epc;
@@ -225,7 +265,11 @@ static int pci_epf_test_write(struct pci_epf_test *epf_test)
 	get_random_bytes(buf, reg->size);
 	reg->checksum = crc32_le(~0, buf, reg->size);
 
+	ktime_get_ts64(&start);
 	memcpy_toio(dst_addr, buf, reg->size);
+	ktime_get_ts64(&end);
+
+	pci_epf_test_print_rate("WRITE", reg->size, &start, &end, false);
 
 	/*
 	 * wait 1ms inorder for the write to complete. Without this delay L3
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 36/50] PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (34 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 35/50] PCI: endpoint: functions/pci-epf-test: Print throughput information Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 37/50] arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST Lad Prabhakar
                   ` (15 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2731 bytes --]

commit a18f4b6ea50b81e28bd05381883a531ab345f753 upstream.

This commit renames pcie-rcar.c to pcie-rcar-host.c in preparation for
adding support for endpoint mode. CONFIG_PCIE_RCAR is kept so that arm64
defconfig change can be a separate patch.

With this patch both config options PCIE_RCAR and PCIE_RCAR_HOST will be
available but PCIE_RCAR internally selects PCIE_RCAR_HOST so that bisect
builds wont be affected.

Link: https://lore.kernel.org/r/1588854799-13710-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/Kconfig                         | 10 ++++++++++
 drivers/pci/controller/Makefile                        |  2 +-
 .../pci/controller/{pcie-rcar.c => pcie-rcar-host.c}   |  0
 3 files changed, 11 insertions(+), 1 deletion(-)
 rename drivers/pci/controller/{pcie-rcar.c => pcie-rcar-host.c} (100%)

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 028b287466fb..6a80ee98aab9 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -84,8 +84,18 @@ config PCIE_RCAR
 	bool "Renesas R-Car PCIe controller"
 	depends on ARCH_RENESAS || COMPILE_TEST
 	depends on PCI_MSI_IRQ_DOMAIN
+	select PCIE_RCAR_HOST
 	help
 	  Say Y here if you want PCIe controller support on R-Car SoCs.
+	  This option will be removed after arm64 defconfig is updated.
+
+config PCIE_RCAR_HOST
+	bool "Renesas R-Car PCIe host controller"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	depends on PCI_MSI_IRQ_DOMAIN
+	help
+	  Say Y here if you want PCIe controller support on R-Car SoCs in host
+	  mode.
 
 config PCI_HOST_COMMON
 	bool
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index d56a507495c5..ad0112741d6b 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
-obj-$(CONFIG_PCIE_RCAR) += pcie-rcar.o
+obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar-host.o
 obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
 obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar-host.c
similarity index 100%
rename from drivers/pci/controller/pcie-rcar.c
rename to drivers/pci/controller/pcie-rcar-host.c
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 37/50] arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (35 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 36/50] PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file Lad Prabhakar
                   ` (14 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1204 bytes --]

commit fecc5cfcd55f7aacc483726c405a951bd6aaaf2e upstream.

config option PCIE_RCAR internally selects PCIE_RCAR_HOST which builds
the same driver. So this patch renames CONFIG_PCIE_RCAR to
CONFIG_PCIE_RCAR_HOST so that PCIE_RCAR can be safely dropped from
Kconfig file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1589494238-2933-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to defconfig]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ef20c1f308fa..ace1b58f3ff5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -77,7 +77,7 @@ CONFIG_HOTPLUG_PCI=y
 CONFIG_HOTPLUG_PCI_ACPI=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PCI_TEGRA=y
-CONFIG_PCIE_RCAR=y
+CONFIG_PCIE_RCAR_HOST=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_XGENE=y
 CONFIG_PCI_HOST_THUNDER_PEM=y
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (36 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 37/50] arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-21 19:06   ` Pavel Machek
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 39/50] PCI: rcar: Fix calculating mask for PCIEPAMR register Lad Prabhakar
                   ` (13 subsequent siblings)
  51 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 8269 bytes --]

commit 78a0d7f2f5a31357bce68012d886507b4cf33598 upstream.

Move shareable code to common file pcie-rcar.c and the #defines to
pcie-rcar.h so that the common code can be reused with endpoint driver.
There are no functional changes with this patch for the host controller
driver.

Link: https://lore.kernel.org/r/1588854799-13710-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[PL: Dropped changes to pcie-rcar-host.c as it doesnt apply cleanly and
manually applying the changes would result in huge change]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-rcar.c | 117 ++++++++++++++++++++++++++
 drivers/pci/controller/pcie-rcar.h | 131 +++++++++++++++++++++++++++++
 2 files changed, 248 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-rcar.c
 create mode 100644 drivers/pci/controller/pcie-rcar.h

diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
new file mode 100644
index 000000000000..cf8840d180c3
--- /dev/null
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe driver for Renesas R-Car SoCs
+ *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
+ *
+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
+ */
+
+#include <linux/delay.h>
+#include <linux/pci.h>
+
+#include "pcie-rcar.h"
+
+void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg)
+{
+	writel(val, pcie->base + reg);
+}
+
+u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg)
+{
+	return readl(pcie->base + reg);
+}
+
+void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
+{
+	unsigned int shift = BITS_PER_BYTE * (where & 3);
+	u32 val = rcar_pci_read_reg(pcie, where & ~3);
+
+	val &= ~(mask << shift);
+	val |= data << shift;
+	rcar_pci_write_reg(pcie, val, where & ~3);
+}
+
+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie)
+{
+	unsigned int timeout = 10;
+
+	while (timeout--) {
+		if (rcar_pci_read_reg(pcie, PCIEPHYSR) & PHYRDY)
+			return 0;
+
+		msleep(5);
+	}
+
+	return -ETIMEDOUT;
+}
+
+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
+{
+	unsigned int timeout = 10000;
+
+	while (timeout--) {
+		if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
+			return 0;
+
+		udelay(5);
+		cpu_relax();
+	}
+
+	return -ETIMEDOUT;
+}
+
+void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
+			    struct resource_entry *window)
+{
+	/* Setup PCIe address space mappings for each resource */
+	struct resource *res = window->res;
+	resource_size_t res_start;
+	resource_size_t size;
+	u32 mask;
+
+	rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
+
+	/*
+	 * The PAMR mask is calculated in units of 128Bytes, which
+	 * keeps things pretty simple.
+	 */
+	size = resource_size(res);
+	mask = (roundup_pow_of_two(size) / SZ_128) - 1;
+	rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
+
+	if (res->flags & IORESOURCE_IO)
+		res_start = pci_pio_to_address(res->start) - window->offset;
+	else
+		res_start = res->start - window->offset;
+
+	rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
+	rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
+			   PCIEPALR(win));
+
+	/* First resource is for IO */
+	mask = PAR_ENABLE;
+	if (res->flags & IORESOURCE_IO)
+		mask |= IO_SPACE;
+
+	rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
+}
+
+void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
+			   u64 pci_addr, u64 flags, int idx, bool host)
+{
+	/*
+	 * Set up 64-bit inbound regions as the range parser doesn't
+	 * distinguish between 32 and 64-bit types.
+	 */
+	if (host)
+		rcar_pci_write_reg(pcie, lower_32_bits(pci_addr),
+				   PCIEPRAR(idx));
+	rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
+	rcar_pci_write_reg(pcie, flags, PCIELAMR(idx));
+
+	if (host)
+		rcar_pci_write_reg(pcie, upper_32_bits(pci_addr),
+				   PCIEPRAR(idx + 1));
+	rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx + 1));
+	rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
+}
diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h
new file mode 100644
index 000000000000..97640e16af58
--- /dev/null
+++ b/drivers/pci/controller/pcie-rcar.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * PCIe driver for Renesas R-Car SoCs
+ *  Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
+ *
+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
+ */
+
+#ifndef _PCIE_RCAR_H
+#define _PCIE_RCAR_H
+
+#define PCIECAR			0x000010
+#define PCIECCTLR		0x000018
+#define  CONFIG_SEND_ENABLE	BIT(31)
+#define  TYPE0			(0 << 8)
+#define  TYPE1			BIT(8)
+#define PCIECDR			0x000020
+#define PCIEMSR			0x000028
+#define PCIEINTXR		0x000400
+#define PCIEPHYSR		0x0007f0
+#define  PHYRDY			BIT(0)
+#define PCIEMSITXR		0x000840
+
+/* Transfer control */
+#define PCIETCTLR		0x02000
+#define  DL_DOWN		BIT(3)
+#define  CFINIT			BIT(0)
+#define PCIETSTR		0x02004
+#define  DATA_LINK_ACTIVE	BIT(0)
+#define PCIEERRFR		0x02020
+#define  UNSUPPORTED_REQUEST	BIT(4)
+#define PCIEMSIFR		0x02044
+#define PCIEMSIALR		0x02048
+#define  MSIFE			BIT(0)
+#define PCIEMSIAUR		0x0204c
+#define PCIEMSIIER		0x02050
+
+/* root port address */
+#define PCIEPRAR(x)		(0x02080 + ((x) * 0x4))
+
+/* local address reg & mask */
+#define PCIELAR(x)		(0x02200 + ((x) * 0x20))
+#define PCIELAMR(x)		(0x02208 + ((x) * 0x20))
+#define  LAM_PREFETCH		BIT(3)
+#define  LAM_64BIT		BIT(2)
+#define  LAR_ENABLE		BIT(1)
+
+/* PCIe address reg & mask */
+#define PCIEPALR(x)		(0x03400 + ((x) * 0x20))
+#define PCIEPAUR(x)		(0x03404 + ((x) * 0x20))
+#define PCIEPAMR(x)		(0x03408 + ((x) * 0x20))
+#define PCIEPTCTLR(x)		(0x0340c + ((x) * 0x20))
+#define  PAR_ENABLE		BIT(31)
+#define  IO_SPACE		BIT(8)
+
+/* Configuration */
+#define PCICONF(x)		(0x010000 + ((x) * 0x4))
+#define PMCAP(x)		(0x010040 + ((x) * 0x4))
+#define EXPCAP(x)		(0x010070 + ((x) * 0x4))
+#define VCCAP(x)		(0x010100 + ((x) * 0x4))
+
+/* link layer */
+#define IDSETR1			0x011004
+#define TLCTLR			0x011048
+#define MACSR			0x011054
+#define  SPCHGFIN		BIT(4)
+#define  SPCHGFAIL		BIT(6)
+#define  SPCHGSUC		BIT(7)
+#define  LINK_SPEED		(0xf << 16)
+#define  LINK_SPEED_2_5GTS	(1 << 16)
+#define  LINK_SPEED_5_0GTS	(2 << 16)
+#define MACCTLR			0x011058
+#define  MACCTLR_NFTS_MASK	GENMASK(23, 16)	/* The name is from SH7786 */
+#define  SPEED_CHANGE		BIT(24)
+#define  SCRAMBLE_DISABLE	BIT(27)
+#define  LTSMDIS		BIT(31)
+#define  MACCTLR_INIT_VAL	(LTSMDIS | MACCTLR_NFTS_MASK)
+#define PMSR			0x01105c
+#define MACS2R			0x011078
+#define MACCGSPSETR		0x011084
+#define  SPCNGRSN		BIT(31)
+
+/* R-Car H1 PHY */
+#define H1_PCIEPHYADRR		0x04000c
+#define  WRITE_CMD		BIT(16)
+#define  PHY_ACK		BIT(24)
+#define  RATE_POS		12
+#define  LANE_POS		8
+#define  ADR_POS		0
+#define H1_PCIEPHYDOUTR		0x040014
+
+/* R-Car Gen2 PHY */
+#define GEN2_PCIEPHYADDR	0x780
+#define GEN2_PCIEPHYDATA	0x784
+#define GEN2_PCIEPHYCTRL	0x78c
+
+#define INT_PCI_MSI_NR		32
+
+#define RCONF(x)		(PCICONF(0) + (x))
+#define RPMCAP(x)		(PMCAP(0) + (x))
+#define REXPCAP(x)		(EXPCAP(0) + (x))
+#define RVCCAP(x)		(VCCAP(0) + (x))
+
+#define PCIE_CONF_BUS(b)	(((b) & 0xff) << 24)
+#define PCIE_CONF_DEV(d)	(((d) & 0x1f) << 19)
+#define PCIE_CONF_FUNC(f)	(((f) & 0x7) << 16)
+
+#define RCAR_PCI_MAX_RESOURCES	4
+#define MAX_NR_INBOUND_MAPS	6
+
+struct rcar_pcie {
+	struct device		*dev;
+	void __iomem		*base;
+};
+
+enum {
+	RCAR_PCI_ACCESS_READ,
+	RCAR_PCI_ACCESS_WRITE,
+};
+
+void rcar_pci_write_reg(struct rcar_pcie *pcie, u32 val, unsigned int reg);
+u32 rcar_pci_read_reg(struct rcar_pcie *pcie, unsigned int reg);
+void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data);
+int rcar_pcie_wait_for_phyrdy(struct rcar_pcie *pcie);
+int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie);
+void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
+			    struct resource_entry *window);
+void rcar_pcie_set_inbound(struct rcar_pcie *pcie, u64 cpu_addr,
+			   u64 pci_addr, u64 flags, int idx, bool host);
+
+#endif
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 39/50] PCI: rcar: Fix calculating mask for PCIEPAMR register
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (37 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 40/50] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar
                   ` (12 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1275 bytes --]

commit 328263687148bebf0d5daf5d06bcc2a46f3d7b0a upstream.

The mask value was calculated incorrectly for PCIEPAMR register if the
size was less than 128 bytes. Fix this issue by adding a check on size.

Link: https://lore.kernel.org/r/1588854799-13710-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/pcie-rcar.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
index cf8840d180c3..7583699ef7b6 100644
--- a/drivers/pci/controller/pcie-rcar.c
+++ b/drivers/pci/controller/pcie-rcar.c
@@ -76,7 +76,10 @@ void rcar_pcie_set_outbound(struct rcar_pcie *pcie, int win,
 	 * keeps things pretty simple.
 	 */
 	size = resource_size(res);
-	mask = (roundup_pow_of_two(size) / SZ_128) - 1;
+	if (size > 128)
+		mask = (roundup_pow_of_two(size) / SZ_128) - 1;
+	else
+		mask = 0x0;
 	rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
 
 	if (res->flags & IORESOURCE_IO)
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 40/50] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (38 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 39/50] PCI: rcar: Fix calculating mask for PCIEPAMR register Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support Lad Prabhakar
                   ` (11 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2878 bytes --]

commit 4c0f80920923f1033e9fe048f44b6e1ffe18c58d upstream.

This patch adds the bindings for the R-Car PCIe endpoint driver.

Link: https://lore.kernel.org/r/1588854799-13710-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/pci/rcar-pci-ep.yaml  | 77 +++++++++++++++++++
 1 file changed, 77 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
new file mode 100644
index 000000000000..aa483c7f27fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Renesas Electronics Europe GmbH - https://www.renesas.com/eu/en/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/rcar-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car PCIe Endpoint
+
+maintainers:
+  - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
+
+properties:
+  compatible:
+    items:
+      - const: renesas,r8a774c0-pcie-ep
+      - const: renesas,rcar-gen3-pcie-ep
+
+  reg:
+    maxItems: 5
+
+  reg-names:
+    items:
+      - const: apb-base
+      - const: memory0
+      - const: memory1
+      - const: memory2
+      - const: memory3
+
+  power-domains:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: pcie
+
+  max-functions:
+    minimum: 1
+    maximum: 1
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - resets
+  - power-domains
+  - clocks
+  - clock-names
+  - max-functions
+
+examples:
+  - |
+    #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
+    #include <dt-bindings/power/r8a774c0-sysc.h>
+
+     pcie0_ep: pcie-ep@fe000000 {
+            compatible = "renesas,r8a774c0-pcie-ep",
+                         "renesas,rcar-gen3-pcie-ep";
+            reg = <0xfe000000 0x80000>,
+                  <0xfe100000 0x100000>,
+                  <0xfe200000 0x200000>,
+                  <0x30000000 0x8000000>,
+                  <0x38000000 0x8000000>;
+            reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+            resets = <&cpg 319>;
+            power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+            clocks = <&cpg CPG_MOD 319>;
+            clock-names = "pcie";
+            max-functions = /bits/ 8 <1>;
+    };
-- 
2.17.1


[-- Attachment #2: Type: text/plain, Size: 420 bytes --]


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (39 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 40/50] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-14  9:22   ` Pavel Machek
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 42/50] arm64: defconfig: Enable R-Car PCIe endpoint driver Lad Prabhakar
                   ` (10 subsequent siblings)
  51 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 17873 bytes --]

commit 2a6d0d63d99956a66f6605832f11755d74a41951 upstream.

Add support for R-Car PCIe controller to work in endpoint mode.

Link: https://lore.kernel.org/r/1588854799-13710-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[PL: Manually applied changes to Makefile]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/pci/controller/Kconfig        |   8 +
 drivers/pci/controller/Makefile       |   1 +
 drivers/pci/controller/pcie-rcar-ep.c | 563 ++++++++++++++++++++++++++
 drivers/pci/controller/pcie-rcar.h    |   9 +
 4 files changed, 581 insertions(+)
 create mode 100644 drivers/pci/controller/pcie-rcar-ep.c

diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
index 6a80ee98aab9..c7a0b613d16d 100644
--- a/drivers/pci/controller/Kconfig
+++ b/drivers/pci/controller/Kconfig
@@ -97,6 +97,14 @@ config PCIE_RCAR_HOST
 	  Say Y here if you want PCIe controller support on R-Car SoCs in host
 	  mode.
 
+config PCIE_RCAR_EP
+	bool "Renesas R-Car PCIe endpoint controller"
+	depends on ARCH_RENESAS || COMPILE_TEST
+	depends on PCI_ENDPOINT
+	help
+	  Say Y here if you want PCIe controller support on R-Car SoCs in
+	  endpoint mode.
+
 config PCI_HOST_COMMON
 	bool
 	select PCI_ECAM
diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile
index ad0112741d6b..19e7dfc961f6 100644
--- a/drivers/pci/controller/Makefile
+++ b/drivers/pci/controller/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 obj-$(CONFIG_PCIE_RCAR_HOST) += pcie-rcar-host.o
+obj-$(CONFIG_PCIE_RCAR_EP) += pcie-rcar.o pcie-rcar-ep.o
 obj-$(CONFIG_PCI_HOST_COMMON) += pci-host-common.o
 obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
 obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
new file mode 100644
index 000000000000..b4a288e24aaf
--- /dev/null
+++ b/drivers/pci/controller/pcie-rcar-ep.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe endpoint driver for Renesas R-Car SoCs
+ *  Copyright (c) 2020 Renesas Electronics Europe GmbH
+ *
+ * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/pci.h>
+#include <linux/pci-epc.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+
+#include "pcie-rcar.h"
+
+#define RCAR_EPC_MAX_FUNCTIONS		1
+
+/* Structure representing the PCIe interface */
+struct rcar_pcie_endpoint {
+	struct rcar_pcie	pcie;
+	phys_addr_t		*ob_mapped_addr;
+	struct pci_epc_mem_window *ob_window;
+	u8			max_functions;
+	unsigned int		bar_to_atu[MAX_NR_INBOUND_MAPS];
+	unsigned long		*ib_window_map;
+	u32			num_ib_windows;
+	u32			num_ob_windows;
+};
+
+static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie)
+{
+	u32 val;
+
+	rcar_pci_write_reg(pcie, 0, PCIETCTLR);
+
+	/* Set endpoint mode */
+	rcar_pci_write_reg(pcie, 0, PCIEMSR);
+
+	/* Initialize default capabilities. */
+	rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
+	rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
+		   PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ENDPOINT << 4);
+	rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
+		   PCI_HEADER_TYPE_NORMAL);
+
+	/* Write out the physical slot number = 0 */
+	rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
+
+	val = rcar_pci_read_reg(pcie, EXPCAP(1));
+	/* device supports fixed 128 bytes MPSS */
+	val &= ~GENMASK(2, 0);
+	rcar_pci_write_reg(pcie, val, EXPCAP(1));
+
+	val = rcar_pci_read_reg(pcie, EXPCAP(2));
+	/* read requests size 128 bytes */
+	val &= ~GENMASK(14, 12);
+	/* payload size 128 bytes */
+	val &= ~GENMASK(7, 5);
+	rcar_pci_write_reg(pcie, val, EXPCAP(2));
+
+	/* Set target link speed to 5.0 GT/s */
+	rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS,
+		   PCI_EXP_LNKSTA_CLS_5_0GB);
+
+	/* Set the completion timer timeout to the maximum 50ms. */
+	rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
+
+	/* Terminate list of capabilities (Next Capability Offset=0) */
+	rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
+
+	/* flush modifications */
+	wmb();
+}
+
+static int rcar_pcie_ep_get_window(struct rcar_pcie_endpoint *ep,
+				   phys_addr_t addr)
+{
+	int i;
+
+	for (i = 0; i < ep->num_ob_windows; i++)
+		if (ep->ob_window[i].phys_base == addr)
+			return i;
+
+	return -EINVAL;
+}
+
+static int rcar_pcie_parse_outbound_ranges(struct rcar_pcie_endpoint *ep,
+					   struct platform_device *pdev)
+{
+	struct rcar_pcie *pcie = &ep->pcie;
+	char outbound_name[10];
+	struct resource *res;
+	unsigned int i = 0;
+
+	ep->num_ob_windows = 0;
+	for (i = 0; i < RCAR_PCI_MAX_RESOURCES; i++) {
+		sprintf(outbound_name, "memory%u", i);
+		res = platform_get_resource_byname(pdev,
+						   IORESOURCE_MEM,
+						   outbound_name);
+		if (!res) {
+			dev_err(pcie->dev, "missing outbound window %u\n", i);
+			return -EINVAL;
+		}
+		if (!devm_request_mem_region(&pdev->dev, res->start,
+					     resource_size(res),
+					     outbound_name)) {
+			dev_err(pcie->dev, "Cannot request memory region %s.\n",
+				outbound_name);
+			return -EIO;
+		}
+
+		ep->ob_window[i].phys_base = res->start;
+		ep->ob_window[i].size = resource_size(res);
+		/* controller doesn't support multiple allocation
+		 * from same window, so set page_size to window size
+		 */
+		ep->ob_window[i].page_size = resource_size(res);
+	}
+	ep->num_ob_windows = i;
+
+	return 0;
+}
+
+static int rcar_pcie_ep_get_pdata(struct rcar_pcie_endpoint *ep,
+				  struct platform_device *pdev)
+{
+	struct rcar_pcie *pcie = &ep->pcie;
+	struct pci_epc_mem_window *window;
+	struct device *dev = pcie->dev;
+	struct resource res;
+	int err;
+
+	err = of_address_to_resource(dev->of_node, 0, &res);
+	if (err)
+		return err;
+	pcie->base = devm_ioremap_resource(dev, &res);
+	if (IS_ERR(pcie->base))
+		return PTR_ERR(pcie->base);
+
+	ep->ob_window = devm_kcalloc(dev, RCAR_PCI_MAX_RESOURCES,
+				     sizeof(*window), GFP_KERNEL);
+	if (!ep->ob_window)
+		return -ENOMEM;
+
+	rcar_pcie_parse_outbound_ranges(ep, pdev);
+
+	err = of_property_read_u8(dev->of_node, "max-functions",
+				  &ep->max_functions);
+	if (err < 0 || ep->max_functions > RCAR_EPC_MAX_FUNCTIONS)
+		ep->max_functions = RCAR_EPC_MAX_FUNCTIONS;
+
+	return 0;
+}
+
+static int rcar_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
+				     struct pci_epf_header *hdr)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	struct rcar_pcie *pcie = &ep->pcie;
+	u32 val;
+
+	if (!fn)
+		val = hdr->vendorid;
+	else
+		val = rcar_pci_read_reg(pcie, IDSETR0);
+	val |= hdr->deviceid << 16;
+	rcar_pci_write_reg(pcie, val, IDSETR0);
+
+	val = hdr->revid;
+	val |= hdr->progif_code << 8;
+	val |= hdr->subclass_code << 16;
+	val |= hdr->baseclass_code << 24;
+	rcar_pci_write_reg(pcie, val, IDSETR1);
+
+	if (!fn)
+		val = hdr->subsys_vendor_id;
+	else
+		val = rcar_pci_read_reg(pcie, SUBIDSETR);
+	val |= hdr->subsys_id << 16;
+	rcar_pci_write_reg(pcie, val, SUBIDSETR);
+
+	if (hdr->interrupt_pin > PCI_INTERRUPT_INTA)
+		return -EINVAL;
+	val = rcar_pci_read_reg(pcie, PCICONF(15));
+	val |= (hdr->interrupt_pin << 8);
+	rcar_pci_write_reg(pcie, val, PCICONF(15));
+
+	return 0;
+}
+
+static int rcar_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
+				struct pci_epf_bar *epf_bar)
+{
+	int flags = epf_bar->flags | LAR_ENABLE | LAM_64BIT;
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	u64 size = 1ULL << fls64(epf_bar->size - 1);
+	dma_addr_t cpu_addr = epf_bar->phys_addr;
+	enum pci_barno bar = epf_bar->barno;
+	struct rcar_pcie *pcie = &ep->pcie;
+	u32 mask;
+	int idx;
+	int err;
+
+	idx = find_first_zero_bit(ep->ib_window_map, ep->num_ib_windows);
+	if (idx >= ep->num_ib_windows) {
+		dev_err(pcie->dev, "no free inbound window\n");
+		return -EINVAL;
+	}
+
+	if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO)
+		flags |= IO_SPACE;
+
+	ep->bar_to_atu[bar] = idx;
+	/* use 64-bit BARs */
+	set_bit(idx, ep->ib_window_map);
+	set_bit(idx + 1, ep->ib_window_map);
+
+	if (cpu_addr > 0) {
+		unsigned long nr_zeros = __ffs64(cpu_addr);
+		u64 alignment = 1ULL << nr_zeros;
+
+		size = min(size, alignment);
+	}
+
+	size = min(size, 1ULL << 32);
+
+	mask = roundup_pow_of_two(size) - 1;
+	mask &= ~0xf;
+
+	rcar_pcie_set_inbound(pcie, cpu_addr,
+			      0x0, mask | flags, idx, false);
+
+	err = rcar_pcie_wait_for_phyrdy(pcie);
+	if (err) {
+		dev_err(pcie->dev, "phy not ready\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void rcar_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
+				   struct pci_epf_bar *epf_bar)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	enum pci_barno bar = epf_bar->barno;
+	u32 atu_index = ep->bar_to_atu[bar];
+
+	rcar_pcie_set_inbound(&ep->pcie, 0x0, 0x0, 0x0, bar, false);
+
+	clear_bit(atu_index, ep->ib_window_map);
+	clear_bit(atu_index + 1, ep->ib_window_map);
+}
+
+static int rcar_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 interrupts)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	struct rcar_pcie *pcie = &ep->pcie;
+	u32 flags;
+
+	flags = rcar_pci_read_reg(pcie, MSICAP(fn));
+	flags |= interrupts << MSICAP0_MMESCAP_OFFSET;
+	rcar_pci_write_reg(pcie, flags, MSICAP(fn));
+
+	return 0;
+}
+
+static int rcar_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	struct rcar_pcie *pcie = &ep->pcie;
+	u32 flags;
+
+	flags = rcar_pci_read_reg(pcie, MSICAP(fn));
+	if (!(flags & MSICAP0_MSIE))
+		return -EINVAL;
+
+	return ((flags & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
+}
+
+static int rcar_pcie_ep_map_addr(struct pci_epc *epc, u8 fn,
+				 phys_addr_t addr, u64 pci_addr, size_t size)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	struct rcar_pcie *pcie = &ep->pcie;
+	struct resource_entry win;
+	struct resource res;
+	int window;
+	int err;
+
+	/* check if we have a link. */
+	err = rcar_pcie_wait_for_dl(pcie);
+	if (err) {
+		dev_err(pcie->dev, "link not up\n");
+		return err;
+	}
+
+	window = rcar_pcie_ep_get_window(ep, addr);
+	if (window < 0) {
+		dev_err(pcie->dev, "failed to get corresponding window\n");
+		return -EINVAL;
+	}
+
+	memset(&win, 0x0, sizeof(win));
+	memset(&res, 0x0, sizeof(res));
+	res.start = pci_addr;
+	res.end = pci_addr + size - 1;
+	res.flags = IORESOURCE_MEM;
+	win.res = &res;
+
+	rcar_pcie_set_outbound(pcie, window, &win);
+
+	ep->ob_mapped_addr[window] = addr;
+
+	return 0;
+}
+
+static void rcar_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
+				    phys_addr_t addr)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+	struct resource_entry win;
+	struct resource res;
+	int idx;
+
+	for (idx = 0; idx < ep->num_ob_windows; idx++)
+		if (ep->ob_mapped_addr[idx] == addr)
+			break;
+
+	if (idx >= ep->num_ob_windows)
+		return;
+
+	memset(&win, 0x0, sizeof(win));
+	memset(&res, 0x0, sizeof(res));
+	win.res = &res;
+	rcar_pcie_set_outbound(&ep->pcie, idx, &win);
+
+	ep->ob_mapped_addr[idx] = 0;
+}
+
+static int rcar_pcie_ep_assert_intx(struct rcar_pcie_endpoint *ep,
+				    u8 fn, u8 intx)
+{
+	struct rcar_pcie *pcie = &ep->pcie;
+	u32 val;
+
+	val = rcar_pci_read_reg(pcie, PCIEMSITXR);
+	if ((val & PCI_MSI_FLAGS_ENABLE)) {
+		dev_err(pcie->dev, "MSI is enabled, cannot assert INTx\n");
+		return -EINVAL;
+	}
+
+	val = rcar_pci_read_reg(pcie, PCICONF(1));
+	if ((val & INTDIS)) {
+		dev_err(pcie->dev, "INTx message transmission is disabled\n");
+		return -EINVAL;
+	}
+
+	val = rcar_pci_read_reg(pcie, PCIEINTXR);
+	if ((val & ASTINTX)) {
+		dev_err(pcie->dev, "INTx is already asserted\n");
+		return -EINVAL;
+	}
+
+	val |= ASTINTX;
+	rcar_pci_write_reg(pcie, val, PCIEINTXR);
+	usleep_range(1000, 1001);
+	val = rcar_pci_read_reg(pcie, PCIEINTXR);
+	val &= ~ASTINTX;
+	rcar_pci_write_reg(pcie, val, PCIEINTXR);
+
+	return 0;
+}
+
+static int rcar_pcie_ep_assert_msi(struct rcar_pcie *pcie,
+				   u8 fn, u8 interrupt_num)
+{
+	u16 msi_count;
+	u32 val;
+
+	/* Check MSI enable bit */
+	val = rcar_pci_read_reg(pcie, MSICAP(fn));
+	if (!(val & MSICAP0_MSIE))
+		return -EINVAL;
+
+	/* Get MSI numbers from MME */
+	msi_count = ((val & MSICAP0_MMESE_MASK) >> MSICAP0_MMESE_OFFSET);
+	msi_count = 1 << msi_count;
+
+	if (!interrupt_num || interrupt_num > msi_count)
+		return -EINVAL;
+
+	val = rcar_pci_read_reg(pcie, PCIEMSITXR);
+	rcar_pci_write_reg(pcie, val | (interrupt_num - 1), PCIEMSITXR);
+
+	return 0;
+}
+
+static int rcar_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
+				  enum pci_epc_irq_type type,
+				  u16 interrupt_num)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+
+	switch (type) {
+	case PCI_EPC_IRQ_LEGACY:
+		return rcar_pcie_ep_assert_intx(ep, fn, 0);
+
+	case PCI_EPC_IRQ_MSI:
+		return rcar_pcie_ep_assert_msi(&ep->pcie, fn, interrupt_num);
+
+	default:
+		return -EINVAL;
+	}
+}
+
+static int rcar_pcie_ep_start(struct pci_epc *epc)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+
+	rcar_pci_write_reg(&ep->pcie, MACCTLR_INIT_VAL, MACCTLR);
+	rcar_pci_write_reg(&ep->pcie, CFINIT, PCIETCTLR);
+
+	return 0;
+}
+
+static void rcar_pcie_ep_stop(struct pci_epc *epc)
+{
+	struct rcar_pcie_endpoint *ep = epc_get_drvdata(epc);
+
+	rcar_pci_write_reg(&ep->pcie, 0, PCIETCTLR);
+}
+
+static const struct pci_epc_features rcar_pcie_epc_features = {
+	.linkup_notifier = false,
+	.msi_capable = true,
+	.msix_capable = false,
+	/* use 64-bit BARs so mark BAR[1,3,5] as reserved */
+	.reserved_bar = 1 << BAR_1 | 1 << BAR_3 | 1 << BAR_5,
+	.bar_fixed_64bit = 1 << BAR_0 | 1 << BAR_2 | 1 << BAR_4,
+	.bar_fixed_size[0] = 128,
+	.bar_fixed_size[2] = 256,
+	.bar_fixed_size[4] = 256,
+};
+
+static const struct pci_epc_features*
+rcar_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
+{
+	return &rcar_pcie_epc_features;
+}
+
+static const struct pci_epc_ops rcar_pcie_epc_ops = {
+	.write_header	= rcar_pcie_ep_write_header,
+	.set_bar	= rcar_pcie_ep_set_bar,
+	.clear_bar	= rcar_pcie_ep_clear_bar,
+	.set_msi	= rcar_pcie_ep_set_msi,
+	.get_msi	= rcar_pcie_ep_get_msi,
+	.map_addr	= rcar_pcie_ep_map_addr,
+	.unmap_addr	= rcar_pcie_ep_unmap_addr,
+	.raise_irq	= rcar_pcie_ep_raise_irq,
+	.start		= rcar_pcie_ep_start,
+	.stop		= rcar_pcie_ep_stop,
+	.get_features	= rcar_pcie_ep_get_features,
+};
+
+static const struct of_device_id rcar_pcie_ep_of_match[] = {
+	{ .compatible = "renesas,r8a774c0-pcie-ep", },
+	{ .compatible = "renesas,rcar-gen3-pcie-ep" },
+	{ },
+};
+
+static int rcar_pcie_ep_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rcar_pcie_endpoint *ep;
+	struct rcar_pcie *pcie;
+	struct pci_epc *epc;
+	int err;
+
+	ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
+	if (!ep)
+		return -ENOMEM;
+
+	pcie = &ep->pcie;
+	pcie->dev = dev;
+
+	pm_runtime_enable(dev);
+	err = pm_runtime_get_sync(dev);
+	if (err < 0) {
+		dev_err(dev, "pm_runtime_get_sync failed\n");
+		goto err_pm_disable;
+	}
+
+	err = rcar_pcie_ep_get_pdata(ep, pdev);
+	if (err < 0) {
+		dev_err(dev, "failed to request resources: %d\n", err);
+		goto err_pm_put;
+	}
+
+	ep->num_ib_windows = MAX_NR_INBOUND_MAPS;
+	ep->ib_window_map =
+			devm_kcalloc(dev, BITS_TO_LONGS(ep->num_ib_windows),
+				     sizeof(long), GFP_KERNEL);
+	if (!ep->ib_window_map) {
+		err = -ENOMEM;
+		dev_err(dev, "failed to allocate memory for inbound map\n");
+		goto err_pm_put;
+	}
+
+	ep->ob_mapped_addr = devm_kcalloc(dev, ep->num_ob_windows,
+					  sizeof(*ep->ob_mapped_addr),
+					  GFP_KERNEL);
+	if (!ep->ob_mapped_addr) {
+		err = -ENOMEM;
+		dev_err(dev, "failed to allocate memory for outbound memory pointers\n");
+		goto err_pm_put;
+	}
+
+	epc = devm_pci_epc_create(dev, &rcar_pcie_epc_ops);
+	if (IS_ERR(epc)) {
+		dev_err(dev, "failed to create epc device\n");
+		err = PTR_ERR(epc);
+		goto err_pm_put;
+	}
+
+	epc->max_functions = ep->max_functions;
+	epc_set_drvdata(epc, ep);
+
+	rcar_pcie_ep_hw_init(pcie);
+
+	err = pci_epc_multi_mem_init(epc, ep->ob_window, ep->num_ob_windows);
+	if (err < 0) {
+		dev_err(dev, "failed to initialize the epc memory space\n");
+		goto err_pm_put;
+	}
+
+	return 0;
+
+err_pm_put:
+	pm_runtime_put(dev);
+
+err_pm_disable:
+	pm_runtime_disable(dev);
+
+	return err;
+}
+
+static struct platform_driver rcar_pcie_ep_driver = {
+	.driver = {
+		.name = "rcar-pcie-ep",
+		.of_match_table = rcar_pcie_ep_of_match,
+		.suppress_bind_attrs = true,
+	},
+	.probe = rcar_pcie_ep_probe,
+};
+builtin_platform_driver(rcar_pcie_ep_driver);
diff --git a/drivers/pci/controller/pcie-rcar.h b/drivers/pci/controller/pcie-rcar.h
index 97640e16af58..d4c698b5f821 100644
--- a/drivers/pci/controller/pcie-rcar.h
+++ b/drivers/pci/controller/pcie-rcar.h
@@ -17,6 +17,7 @@
 #define PCIECDR			0x000020
 #define PCIEMSR			0x000028
 #define PCIEINTXR		0x000400
+#define  ASTINTX		BIT(16)
 #define PCIEPHYSR		0x0007f0
 #define  PHYRDY			BIT(0)
 #define PCIEMSITXR		0x000840
@@ -55,12 +56,20 @@
 
 /* Configuration */
 #define PCICONF(x)		(0x010000 + ((x) * 0x4))
+#define  INTDIS			BIT(10)
 #define PMCAP(x)		(0x010040 + ((x) * 0x4))
+#define MSICAP(x)		(0x010050 + ((x) * 0x4))
+#define  MSICAP0_MSIE		BIT(16)
+#define  MSICAP0_MMESCAP_OFFSET	17
+#define  MSICAP0_MMESE_OFFSET	20
+#define  MSICAP0_MMESE_MASK	GENMASK(22, 20)
 #define EXPCAP(x)		(0x010070 + ((x) * 0x4))
 #define VCCAP(x)		(0x010100 + ((x) * 0x4))
 
 /* link layer */
+#define IDSETR0			0x011000
 #define IDSETR1			0x011004
+#define SUBIDSETR		0x011024
 #define TLCTLR			0x011048
 #define MACSR			0x011054
 #define  SPCHGFIN		BIT(4)
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 42/50] arm64: defconfig: Enable R-Car PCIe endpoint driver
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (40 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 43/50] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1 Lad Prabhakar
                   ` (9 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1576 bytes --]

commit cd8bc7d4eb6608afe78ac51422ef94b7824f1646 upstream.

Enable R-Car PCIe endpoint driver on RZ/G2E board, including enabling
endpoint configurations CONFIG_PCI_ENDPOINT, CONFIG_PCI_ENDPOINT_CONFIGFS,
CONFIG_PCI_EPF_TEST and CONFIG_PCI_ENDPOINT_TEST required to use and test
the driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20200811140357.564-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes to defconfig file]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/configs/defconfig | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ace1b58f3ff5..c8cc683d6e97 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -78,6 +78,7 @@ CONFIG_HOTPLUG_PCI_ACPI=y
 CONFIG_PCI_AARDVARK=y
 CONFIG_PCI_TEGRA=y
 CONFIG_PCIE_RCAR_HOST=y
+CONFIG_PCIE_RCAR_EP=y
 CONFIG_PCI_HOST_GENERIC=y
 CONFIG_PCI_XGENE=y
 CONFIG_PCI_HOST_THUNDER_PEM=y
@@ -88,6 +89,9 @@ CONFIG_PCI_HISI=y
 CONFIG_PCIE_QCOM=y
 CONFIG_PCIE_ARMADA_8K=y
 CONFIG_PCIE_KIRIN=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_PCI_ENDPOINT_CONFIGFS=y
+CONFIG_PCI_EPF_TEST=m
 CONFIG_PCIE_HISI_STB=y
 CONFIG_ARM64_VA_BITS_48=y
 CONFIG_SCHED_MC=y
@@ -194,6 +198,7 @@ CONFIG_BLK_DEV_NBD=m
 CONFIG_VIRTIO_BLK=y
 CONFIG_BLK_DEV_NVME=m
 CONFIG_SRAM=y
+CONFIG_PCI_ENDPOINT_TEST=m
 CONFIG_EEPROM_AT25=m
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 43/50] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (41 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 42/50] arm64: defconfig: Enable R-Car PCIe endpoint driver Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 44/50] arm64: dts: renesas: r8a774c0: Add PCIe EP node Lad Prabhakar
                   ` (8 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1651 bytes --]

commit 2de82ec8667465236e15f8c6af7cecf8da63fc60 upstream.

Document the support for R-Car PCIe EP on R8A774A1 and R8A774B1 SoC
devices.

Also constify "renesas,rcar-gen3-pcie-ep" so that it can be used as
fallback compatible string for R-Car Gen3 and RZ/G2 devices as the
PCIe module is identical.

Link: https://lore.kernel.org/r/20200814173037.17822-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
index aa483c7f27fd..70c45f72ab20 100644
--- a/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/rcar-pci-ep.yaml
@@ -14,8 +14,11 @@ maintainers:
 properties:
   compatible:
     items:
-      - const: renesas,r8a774c0-pcie-ep
-      - const: renesas,rcar-gen3-pcie-ep
+      - enum:
+          - renesas,r8a774a1-pcie-ep     # RZ/G2M
+          - renesas,r8a774b1-pcie-ep     # RZ/G2N
+          - renesas,r8a774c0-pcie-ep     # RZ/G2E
+      - const: renesas,rcar-gen3-pcie-ep # R-Car Gen3 and RZ/G2
 
   reg:
     maxItems: 5
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 44/50] arm64: dts: renesas: r8a774c0: Add PCIe EP node
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (42 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 43/50] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1 Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 45/50] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes Lad Prabhakar
                   ` (7 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1654 bytes --]

commit 0c77ecdcfcd35e97c677e49a8516a0b10c1e8fb7 upstream.

Add PCIe EP node to R8A774C0 (RZ/G2E) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-6-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 7ba934c32696..44d66fcb412d 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1698,6 +1698,25 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie-ep@fe000000 {
+			compatible = "renesas,r8a774c0-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		vspb0: vsp@fe960000 {
 			compatible = "renesas,vsp2";
 			reg = <0 0xfe960000 0 0x8000>;
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 45/50] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (43 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 44/50] arm64: dts: renesas: r8a774c0: Add PCIe EP node Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 46/50] arm64: dts: renesas: r8a774b1: " Lad Prabhakar
                   ` (6 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2348 bytes --]

commit 578450883bb1ff878ac8e3d38060802b222adcbe upstream.

Add PCIe EP nodes to R8A774A1 (RZ/G2M) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 16166f3b66a0..90f5fb49957e 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2115,6 +2115,44 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie-ep@fe000000 {
+			compatible = "renesas,r8a774a1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pciec1_ep: pcie-ep@ee800000 {
+			compatible = "renesas,r8a774a1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xee800000 0 0x80000>,
+			      <0x0 0xee900000 0 0x100000>,
+			      <0x0 0xeea00000 0 0x200000>,
+			      <0x0 0xc0000000 0 0x8000000>,
+			      <0x0 0xc8000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>;
+			clock-names = "pcie";
+			resets = <&cpg 318>;
+			power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		fdp1@fe940000 {
 			compatible = "renesas,fdp1";
 			reg = <0 0xfe940000 0 0x2400>;
-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 46/50] arm64: dts: renesas: r8a774b1: Add PCIe EP nodes
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (44 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 45/50] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 47/50] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller Lad Prabhakar
                   ` (5 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 2348 bytes --]

commit d12d16205f7993da195002eea24b7467deb9ac8c upstream.

Add PCIe EP nodes to R8A774B1 (RZ/G2N) SoC dtsi.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20200814173037.17822-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 62d011107cc5..b48bf2aed612 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1973,6 +1973,44 @@
 			status = "disabled";
 		};
 
+		pciec0_ep: pcie-ep@fe000000 {
+			compatible = "renesas,r8a774b1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xfe000000 0 0x80000>,
+			      <0x0 0xfe100000 0 0x100000>,
+			      <0x0 0xfe200000 0 0x200000>,
+			      <0x0 0x30000000 0 0x8000000>,
+			      <0x0 0x38000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>;
+			clock-names = "pcie";
+			resets = <&cpg 319>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
+		pciec1_ep: pcie-ep@ee800000 {
+			compatible = "renesas,r8a774b1-pcie-ep",
+				     "renesas,rcar-gen3-pcie-ep";
+			reg = <0x0 0xee800000 0 0x80000>,
+			      <0x0 0xee900000 0 0x100000>,
+			      <0x0 0xeea00000 0 0x200000>,
+			      <0x0 0xc0000000 0 0x8000000>,
+			      <0x0 0xc8000000 0 0x8000000>;
+			reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3";
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>;
+			clock-names = "pcie";
+			resets = <&cpg 318>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			status = "disabled";
+		};
+
 		fdp1@fe940000 {
 			compatible = "renesas,fdp1";
 			reg = <0 0xfe940000 0 0x2400>;
-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 47/50] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (45 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 46/50] arm64: dts: renesas: r8a774b1: " Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 48/50] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers Lad Prabhakar
                   ` (4 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1441 bytes --]

commit b03025c57396b23fe2423384c25aa580000e9883 upstream.

Add Renesas R8A774C0 in pci_device_id table so that pci-epf-test can be
used for testing PCIe EP on RZ/G2E.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/r/1589493809-2602-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/misc/pci_endpoint_test.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 7d166f57f624..aff8cbca5d18 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -80,6 +80,8 @@
 #define is_am654_pci_dev(pdev)		\
 		((pdev)->device == PCI_DEVICE_ID_TI_AM654)
 
+#define PCI_DEVICE_ID_RENESAS_R8A774C0		0x002d
+
 static DEFINE_IDA(pci_endpoint_test_ida);
 
 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
@@ -814,6 +816,8 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
 	  .driver_data = (kernel_ulong_t)&am654_data
 	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 48/50] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (46 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 47/50] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 49/50] tools: PCI: Exit with error code when test fails Lad Prabhakar
                   ` (3 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 1778 bytes --]

commit cfb824ddd1c040a7ac65eea3f900f14268e8f383 upstream.

Add Renesas R8A774A1 and R8A774B1 in pci_device_id table so that
pci-epf-test can be used for testing PCIe EP on RZ/G2M and RZ/G2N.

Link: https://lore.kernel.org/r/20200814173037.17822-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[PL: Manually applied changes]
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/misc/pci_endpoint_test.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index aff8cbca5d18..a1083f568d2c 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -80,6 +80,8 @@
 #define is_am654_pci_dev(pdev)		\
 		((pdev)->device == PCI_DEVICE_ID_TI_AM654)
 
+#define PCI_DEVICE_ID_RENESAS_R8A774A1		0x0028
+#define PCI_DEVICE_ID_RENESAS_R8A774B1		0x002b
 #define PCI_DEVICE_ID_RENESAS_R8A774C0		0x002d
 
 static DEFINE_IDA(pci_endpoint_test_ida);
@@ -816,8 +818,9 @@ static const struct pci_device_id pci_endpoint_test_tbl[] = {
 	{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
 	  .driver_data = (kernel_ulong_t)&am654_data
 	},
-	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),
-	},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
+	{ PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
-- 
2.17.1


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* [cip-dev] [RFC PATCH 4.19.y-cip 49/50] tools: PCI: Exit with error code when test fails
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (47 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 48/50] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 50/50] tools: PCI: Fix fd leakage Lad Prabhakar
                   ` (2 subsequent siblings)
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 968 bytes --]

From: Jean-Jacques Hiblot <jjhiblot@ti.com>

commit b71f0a0b1e3fea212a6a5042ced8b48a81738ac9 upstream.

This makes it easier to use pcitest in automated setups.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 tools/pci/pcitest.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
index 4c5be77c211f..b7e3b6a64956 100644
--- a/tools/pci/pcitest.c
+++ b/tools/pci/pcitest.c
@@ -140,6 +140,7 @@ static int run_test(struct pci_test *test)
 	}
 
 	fflush(stdout);
+	return (ret < 0) ? ret : 1 - ret; /* return 0 if test succeeded */
 }
 
 int main(int argc, char **argv)
@@ -228,6 +229,5 @@ int main(int argc, char **argv)
 		return -EINVAL;
 	}
 
-	run_test(test);
-	return 0;
+	return run_test(test);
 }
-- 
2.17.1


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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] [RFC PATCH 4.19.y-cip 50/50] tools: PCI: Fix fd leakage
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (48 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 49/50] tools: PCI: Exit with error code when test fails Lad Prabhakar
@ 2020-10-12 14:19 ` Lad Prabhakar
  2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
  2020-10-14 10:07 ` [cip-dev] " Pavel Machek
  51 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-12 14:19 UTC (permalink / raw)
  To: cip-dev, Nobuhiro Iwamatsu, Pavel Machek; +Cc: Biju Das, Lad Prabhakar


[-- Attachment #1: Type: text/plain, Size: 860 bytes --]

From: Hewenliang <hewenliang4@huawei.com>

commit 3c379a59b4795d7279d38c623e74b9790345a32b upstream.

We should close fd before the return of run_test.

Fixes: 3f2ed8134834 ("tools: PCI: Add a userspace tool to test PCI endpoint")
Signed-off-by: Hewenliang <hewenliang4@huawei.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 tools/pci/pcitest.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
index b7e3b6a64956..9f3d2e584ce4 100644
--- a/tools/pci/pcitest.c
+++ b/tools/pci/pcitest.c
@@ -140,6 +140,7 @@ static int run_test(struct pci_test *test)
 	}
 
 	fflush(stdout);
+	close(fd);
 	return (ret < 0) ? ret : 1 - ret; /* return 0 if test succeeded */
 }
 
-- 
2.17.1


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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support Lad Prabhakar
@ 2020-10-14  9:22   ` Pavel Machek
  2020-10-15 16:31     ` Lad Prabhakar
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-14  9:22 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1005 bytes --]

Hi!

> commit 2a6d0d63d99956a66f6605832f11755d74a41951 upstream.
> 
> Add support for R-Car PCIe controller to work in endpoint mode.

> +		ep->ob_window[i].phys_base = res->start;
> +		ep->ob_window[i].size = resource_size(res);
> +		/* controller doesn't support multiple allocation
> +		 * from same window, so set page_size to window size
> +		 */

Comment not according to CodingStyle.

> +	memset(&win, 0x0, sizeof(win));
> +	memset(&res, 0x0, sizeof(res));

Plain 0 would be enough


> +	val |= ASTINTX;
> +	rcar_pci_write_reg(pcie, val, PCIEINTXR);
> +	usleep_range(1000, 1001);
> +	val = rcar_pci_read_reg(pcie, PCIEINTXR);

This is crazy. Either you need exact timing or you don't, but I don't
believe usleep can guarantee microsecond accuracy.

(And you probably don't need it, right?)

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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^ permalink raw reply	[flat|nested] 73+ messages in thread

* [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (49 preceding siblings ...)
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 50/50] tools: PCI: Fix fd leakage Lad Prabhakar
@ 2020-10-14  9:39 ` Pavel Machek
  2020-10-15 16:18   ` Lad Prabhakar
  2020-10-20  7:16   ` Lad Prabhakar
  2020-10-14 10:07 ` [cip-dev] " Pavel Machek
  51 siblings, 2 replies; 73+ messages in thread
From: Pavel Machek @ 2020-10-14  9:39 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1892 bytes --]

Hi!

> This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> RZ/G2x platforms.

I quickly went through a series and code seems reasonably nice.

> * Since the changes are huge I am sending the patches as RFC.

And yes, it is quite big, which might be a problem. OTOH only Renesas
seems to have PCIe EP drivers enabled in their CIP defconfigs, so
there's good chance noone else in CIP project is using this code.

[If someone else _is_ using it or is considering using it, please
speak up.]

Could we get better explanation for 24/ of the series? spinlock is
okay as long as code inside does not sleep, does not neccessarily have
to do with interrupts.

Should 30/ and 31/ be submitted to stable?

> * Required EP framework changes and fixes are ported as well.
> * All the patches have been cheery picked from upstream kernel.
> * Patches [43, 44, 45, 46, 48]/50 are picked from linux-next.

Ok, so we definitely want them in upstream, not in -next. And it might
be good to wait a bit after merge, so it gets some testing in upstream.

> * I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
>   this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
>   for suggestions if this can be handled differently.
> * In patch 37/48 I have dropped the changes for host driver as the patch
>   doesn't apply cleanly and manually applying it was resulting in a
>   big diff.

Let me take a look at these in bigger detail.

> * As the changes touches three other controller drivers I have build tested them
>   as done similarly while upstreaming R-Car Gen3 PCIe EP driver.

Will this be tested somehow by our automated tests?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
                   ` (50 preceding siblings ...)
  2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
@ 2020-10-14 10:07 ` Pavel Machek
  2020-10-15 16:27   ` Lad Prabhakar
  51 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-14 10:07 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1298 bytes --]

Hi!

> * I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
>   this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
>   for suggestions if this can be handled differently.
> * In patch 37/48 I have dropped the changes for host driver as the patch
>   doesn't apply cleanly and manually applying it was resulting in a
>   big diff.

I have no good ideas how to avoid rename.

Given the change in locking previously in the series, manual review of
changes in this area might be good idea, anyway.

In 4.19, there were 75 patches in this area so far, and 5 patches that
would reject due to the rename.

pavel@amd:~/cip/krc$ git log --pretty=oneline v4.19.. drivers/pci/controller/ | wc -l
75
pavel@amd:~/cip/krc$ git log --pretty=oneline v4.19.. drivers/pci/controller/pcie-rcar*.c | wc -l
5

...so we'll get a bit of additional workload from this. It would be
more scary if there were -rt specific changes in this area, but
hopefully there are none.

I expect that you are willing to help if -stable or -rt introduces
conflicting patches in this area?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
@ 2020-10-15 16:18   ` Lad Prabhakar
  2020-10-20  7:16   ` Lad Prabhakar
  1 sibling, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-15 16:18 UTC (permalink / raw)
  To: cip-dev; +Cc: Nobuhiro Iwamatsu, Pavel Machek, Biju Das


[-- Attachment #1: Type: text/plain, Size: 3372 bytes --]

Hi Pavel,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: 14 October 2020 10:39
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and
> RZ/G2x
>
> Hi!
>
> > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > RZ/G2x platforms.
>
> I quickly went through a series and code seems reasonably nice.
>
Thank you for the review. That’s a relief 😊

> > * Since the changes are huge I am sending the patches as RFC.
>
> And yes, it is quite big, which might be a problem. OTOH only Renesas
> seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> there's good chance noone else in CIP project is using this code.
>
Fingers crossed.

> [If someone else _is_ using it or is considering using it, please
> speak up.]
>
> Could we get better explanation for 24/ of the series? spinlock is
> okay as long as code inside does not sleep, does not neccessarily have
> to do with interrupts.
>
Sure this was cherry picked from upstream I haven’t modified the description. Moreover this I had include because the subsequent patches could apply cleanly.

Do want me to just elaborate the commit message you mean ?

> Should 30/ and 31/ be submitted to stable?
>
Yes I do agree.

> > * Required EP framework changes and fixes are ported as well.
> > * All the patches have been cheery picked from upstream kernel.
> > * Patches [43, 44, 45, 46, 48]/50 are picked from linux-next.
>
> Ok, so we definitely want them in upstream, not in -next. And it might
> be good to wait a bit after merge, so it gets some testing in upstream.
>
Sure Ill wait for them, (fyi these are just dt binding documentation and PCI-ID addition patches)

> > * I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
> >   this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
> >   for suggestions if this can be handled differently.
> > * In patch 37/48 I have dropped the changes for host driver as the patch
> >   doesn't apply cleanly and manually applying it was resulting in a
> >   big diff.
>
> Let me take a look at these in bigger detail.
>
Sure.

> > * As the changes touches three other controller drivers I have build tested them
> >   as done similarly while upstreaming R-Car Gen3 PCIe EP driver.
>
> Will this be tested somehow by our automated tests?
>
You mean the R-Car Gen3 PCIe EP driver ?

Cheers,
Prabhakar

> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-14 10:07 ` [cip-dev] " Pavel Machek
@ 2020-10-15 16:27   ` Lad Prabhakar
  0 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-15 16:27 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 2312 bytes --]

Hi Pavel,

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 14 October 2020 11:08
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
>
> Hi!
>
> > * I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
> >   this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
> >   for suggestions if this can be handled differently.
> > * In patch 37/48 I have dropped the changes for host driver as the patch
> >   doesn't apply cleanly and manually applying it was resulting in a
> >   big diff.
>
> I have no good ideas how to avoid rename.
>
> Given the change in locking previously in the series, manual review of
> changes in this area might be good idea, anyway.
>
The locking changes are wrt EPF framework anyway.  OK so I assume you are happy to manual changes to PCIe host driver while posting non RFC version.

> In 4.19, there were 75 patches in this area so far, and 5 patches that
> would reject due to the rename.
>
> pavel@amd:~/cip/krc$ git log --pretty=oneline v4.19.. drivers/pci/controller/ | wc -l
> 75
> pavel@amd:~/cip/krc$ git log --pretty=oneline v4.19.. drivers/pci/controller/pcie-rcar*.c | wc -l
> 5
>
> ...so we'll get a bit of additional workload from this. It would be
> more scary if there were -rt specific changes in this area, but
> hopefully there are none.
>
> I expect that you are willing to help if -stable or -rt introduces
> conflicting patches in this area?
>
indeed.

Cheers,
Prabhakar

> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
  2020-10-14  9:22   ` Pavel Machek
@ 2020-10-15 16:31     ` Lad Prabhakar
  2020-10-15 18:01       ` Pavel Machek
  0 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-15 16:31 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 2062 bytes --]

Hi Pavel,

Thank you for the review.

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 14 October 2020 10:22
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
>
> Hi!
>
> > commit 2a6d0d63d99956a66f6605832f11755d74a41951 upstream.
> >
> > Add support for R-Car PCIe controller to work in endpoint mode.
>
> > +ep->ob_window[i].phys_base = res->start;
> > +ep->ob_window[i].size = resource_size(res);
> > +/* controller doesn't support multiple allocation
> > + * from same window, so set page_size to window size
> > + */
>
> Comment not according to CodingStyle.
>
Yep
> > +memset(&win, 0x0, sizeof(win));
> > +memset(&res, 0x0, sizeof(res));
>
> Plain 0 would be enough
>
Agreed.

Ill post patches upstream to fix this and then backport or do you want me to do the changes in place ?
>
> > +val |= ASTINTX;
> > +rcar_pci_write_reg(pcie, val, PCIEINTXR);
> > +usleep_range(1000, 1001);
> > +val = rcar_pci_read_reg(pcie, PCIEINTXR);
>
> This is crazy. Either you need exact timing or you don't, but I don't
> believe usleep can guarantee microsecond accuracy.
>
> (And you probably don't need it, right?)
>
Indeed a sleep is needed but checkpatch complains about it so usleep_range() was added.

Cheers,
Prabhakar

> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

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^ permalink raw reply	[flat|nested] 73+ messages in thread

* Re: [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
  2020-10-15 16:31     ` Lad Prabhakar
@ 2020-10-15 18:01       ` Pavel Machek
  2020-10-22 18:23         ` Pavel Machek
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-15 18:01 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1133 bytes --]

Hi!

> > Plain 0 would be enough
> >
> Agreed.
> 
> Ill post patches upstream to fix this and then backport or do you
>want me to do the changes in place ?

Yes, thank you.

> > > +val |= ASTINTX;
> > > +rcar_pci_write_reg(pcie, val, PCIEINTXR);
> > > +usleep_range(1000, 1001);
> > > +val = rcar_pci_read_reg(pcie, PCIEINTXR);
> >
> > This is crazy. Either you need exact timing or you don't, but I don't
> > believe usleep can guarantee microsecond accuracy.
> >
> > (And you probably don't need it, right?)
> >
> Indeed a sleep is needed but checkpatch complains about it so usleep_range() was added.

checkpatch should not be an excuse for crazy code... and this one is
crazy.

Sleep has nowhere near microsecond accuracy. If you can tolerate
bigger delay, feel free to specify reasonable range. But in this case
you probably want "as close as possible to 1msec", and no,
usleep_range is not right primitive for that.

Best regards,
								Pavel

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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^ permalink raw reply	[flat|nested] 73+ messages in thread

* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
  2020-10-15 16:18   ` Lad Prabhakar
@ 2020-10-20  7:16   ` Lad Prabhakar
  2020-10-20 10:34     ` Pavel Machek
  2020-10-20 12:01     ` Pavel Machek
  1 sibling, 2 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-20  7:16 UTC (permalink / raw)
  To: cip-dev, Pavel Machek; +Cc: Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 2716 bytes --]

Hi Pavel,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: 14 October 2020 10:39
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and
> RZ/G2x
> 
> Hi!
> 
> > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > RZ/G2x platforms.
> 
> I quickly went through a series and code seems reasonably nice.
> 
> > * Since the changes are huge I am sending the patches as RFC.
> 
> And yes, it is quite big, which might be a problem. OTOH only Renesas
> seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> there's good chance noone else in CIP project is using this code.
> 
> [If someone else _is_ using it or is considering using it, please
> speak up.]
> 
We haven't received any response yet, is it OK if I send a non RFC version or shall we wait for couple of days more ?

Cheers,
Prabhakar

> Could we get better explanation for 24/ of the series? spinlock is
> okay as long as code inside does not sleep, does not neccessarily have
> to do with interrupts.
> 
> Should 30/ and 31/ be submitted to stable?
> 
> > * Required EP framework changes and fixes are ported as well.
> > * All the patches have been cheery picked from upstream kernel.
> > * Patches [43, 44, 45, 46, 48]/50 are picked from linux-next.
> 
> Ok, so we definitely want them in upstream, not in -next. And it might
> be good to wait a bit after merge, so it gets some testing in upstream.
> 
> > * I was skeptic with patch 36/50 "Rename pcie-rcar.c to pcie-rcar-host.c"
> >   this is required as patch 38/50 adds a new file named pcie-rcar.c. Open
> >   for suggestions if this can be handled differently.
> > * In patch 37/48 I have dropped the changes for host driver as the patch
> >   doesn't apply cleanly and manually applying it was resulting in a
> >   big diff.
> 
> Let me take a look at these in bigger detail.
> 
> > * As the changes touches three other controller drivers I have build tested them
> >   as done similarly while upstreaming R-Car Gen3 PCIe EP driver.
> 
> Will this be tested somehow by our automated tests?
> 
> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-20  7:16   ` Lad Prabhakar
@ 2020-10-20 10:34     ` Pavel Machek
  2020-10-20 12:01     ` Pavel Machek
  1 sibling, 0 replies; 73+ messages in thread
From: Pavel Machek @ 2020-10-20 10:34 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 902 bytes --]

Hi!

> > I quickly went through a series and code seems reasonably nice.
> > 
> > > * Since the changes are huge I am sending the patches as RFC.
> > 
> > And yes, it is quite big, which might be a problem. OTOH only Renesas
> > seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> > there's good chance noone else in CIP project is using this code.
> > 
> > [If someone else _is_ using it or is considering using it, please
> > speak up.]
> > 
> We haven't received any response yet, is it OK if I send a non RFC version or shall we wait for couple of days more ?

No need to retransmit just now. This version is good enough for
review, let me take a closer look and submit some comments.

Best regards,
 								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-20  7:16   ` Lad Prabhakar
  2020-10-20 10:34     ` Pavel Machek
@ 2020-10-20 12:01     ` Pavel Machek
  2020-10-20 13:01       ` Lad Prabhakar
  1 sibling, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-20 12:01 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1068 bytes --]

Hi!

> > > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > > RZ/G2x platforms.
> > 
> > I quickly went through a series and code seems reasonably nice.
> > 
> > > * Since the changes are huge I am sending the patches as RFC.
> > 
> > And yes, it is quite big, which might be a problem. OTOH only Renesas
> > seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> > there's good chance noone else in CIP project is using this code.
> > 
> > [If someone else _is_ using it or is considering using it, please
> > speak up.]
> > 
> We haven't received any response yet, is it OK if I send a non RFC
> version or shall we wait for couple of days more ?

I guess I'd like non-RFC version of patches 1-22 in a series. I
believe it makes sense to add 30, 32, 49, 50 to them, as they are
simple and fix a bug.

Would that work for you?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-20 12:01     ` Pavel Machek
@ 2020-10-20 13:01       ` Lad Prabhakar
  2020-10-20 20:48         ` Pavel Machek
  0 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-20 13:01 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 1792 bytes --]

Hi Pavel,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: 20 October 2020 13:02
> To: cip-dev@lists.cip-project.org
> Cc: Pavel Machek <pavel@denx.de>; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3
> and RZ/G2x
> 
> Hi!
> 
> > > > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > > > RZ/G2x platforms.
> > >
> > > I quickly went through a series and code seems reasonably nice.
> > >
> > > > * Since the changes are huge I am sending the patches as RFC.
> > >
> > > And yes, it is quite big, which might be a problem. OTOH only Renesas
> > > seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> > > there's good chance noone else in CIP project is using this code.
> > >
> > > [If someone else _is_ using it or is considering using it, please
> > > speak up.]
> > >
> > We haven't received any response yet, is it OK if I send a non RFC
> > version or shall we wait for couple of days more ?
> 
> I guess I'd like non-RFC version of patches 1-22 in a series. I
> believe it makes sense to add 30, 32, 49, 50 to them, as they are
> simple and fix a bug.
> 
> Would that work for you?
> 
Sure ill get on posting the above mentioned patches as non-RFC in a series.

How do we tackle with rest of the patches ?

Cheers,
Prabhakar

> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex Lad Prabhakar
@ 2020-10-20 20:43   ` Pavel Machek
  2020-10-20 21:56     ` Lad Prabhakar
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-20 20:43 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 720 bytes --]

Hi!

> commit 3d3248dbd018502f654064c78efcd2e165ab3486 upstream.
> 
> The pci_epc_ops is not intended to be invoked from interrupt context.
> Hence replace spin_lock_irqsave and spin_unlock_irqrestore with
> mutex_lock and mutex_unlock respectively.

Could I get some kind of explanation why this is good idea?

As long as code protected by the locks does not sleep, spinlocks are
okay... (but they should not need "_irqsave" variants).

They are likely to have better performance, too, when protected code
is small and fast.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-20 13:01       ` Lad Prabhakar
@ 2020-10-20 20:48         ` Pavel Machek
  2020-10-20 21:58           ` Lad Prabhakar
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-20 20:48 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1573 bytes --]

Hi!

> > > > > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > > > > RZ/G2x platforms.
> > > >
> > > > I quickly went through a series and code seems reasonably nice.
> > > >
> > > > > * Since the changes are huge I am sending the patches as RFC.
> > > >
> > > > And yes, it is quite big, which might be a problem. OTOH only Renesas
> > > > seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> > > > there's good chance noone else in CIP project is using this code.
> > > >
> > > > [If someone else _is_ using it or is considering using it, please
> > > > speak up.]
> > > >
> > > We haven't received any response yet, is it OK if I send a non RFC
> > > version or shall we wait for couple of days more ?
> > 
> > I guess I'd like non-RFC version of patches 1-22 in a series. I
> > believe it makes sense to add 30, 32, 49, 50 to them, as they are
> > simple and fix a bug.
> > 
> > Would that work for you?
> > 
> Sure ill get on posting the above mentioned patches as non-RFC in a series.
> 
> How do we tackle with rest of the patches ?

Well... I applied this batch. If someone can explain the mutex
vs. spinlock thing, then I guess we can do next batch up to 35...

OTOH I did not go through those patches in detail, and RFC is good
enough for review, so... maybe you can just wait.

Best regards,
    	     	    	   	    	   	      	    Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex
  2020-10-20 20:43   ` Pavel Machek
@ 2020-10-20 21:56     ` Lad Prabhakar
  2020-10-21 18:34       ` Pavel Machek
  0 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-20 21:56 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 1807 bytes --]

Hi Pavel,

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 20 October 2020 21:44
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex
> 
> Hi!
> 
> > commit 3d3248dbd018502f654064c78efcd2e165ab3486 upstream.
> >
> > The pci_epc_ops is not intended to be invoked from interrupt context.
> > Hence replace spin_lock_irqsave and spin_unlock_irqrestore with
> > mutex_lock and mutex_unlock respectively.
> 
> Could I get some kind of explanation why this is good idea?
> 
Apart of one mentioned above other point I would add is on a single core machine mutex_lock/unlock would be good choice.

Also to add the callbacks in controller driver might sleep. For example in raise_irq callback  [1], [2].

> As long as code protected by the locks does not sleep, spinlocks are
> okay... (but they should not need "_irqsave" variants).
> 
> They are likely to have better performance, too, when protected code
> is small and fast.
> 
I do agree with the above two points *if the code isn't sleeping*.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/drivers/pci/controller/pcie-rockchip-ep.c?h=linux-4.19.y-cip#n410
[2] https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/drivers/pci/controller/pcie-cadence-ep.c?h=linux-4.19.y-cip#n310

Cheers,
Prabhakar

> Best regards,
> 								Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x
  2020-10-20 20:48         ` Pavel Machek
@ 2020-10-20 21:58           ` Lad Prabhakar
  0 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-20 21:58 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 2306 bytes --]

Hi Pavel,

> -----Original Message-----
> From: cip-dev@lists.cip-project.org <cip-dev@lists.cip-project.org> On Behalf Of Pavel Machek via lists.cip-project.org
> Sent: 20 October 2020 21:48
> To: cip-dev@lists.cip-project.org
> Cc: Pavel Machek <pavel@denx.de>; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Biju Das <biju.das.jz@bp.renesas.com>
> Subject: Re: [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3
> and RZ/G2x
> 
> Hi!
> 
> > > > > > This patch series adds support for PCIe EP on Renesas R-Car Gen3 and
> > > > > > RZ/G2x platforms.
> > > > >
> > > > > I quickly went through a series and code seems reasonably nice.
> > > > >
> > > > > > * Since the changes are huge I am sending the patches as RFC.
> > > > >
> > > > > And yes, it is quite big, which might be a problem. OTOH only Renesas
> > > > > seems to have PCIe EP drivers enabled in their CIP defconfigs, so
> > > > > there's good chance noone else in CIP project is using this code.
> > > > >
> > > > > [If someone else _is_ using it or is considering using it, please
> > > > > speak up.]
> > > > >
> > > > We haven't received any response yet, is it OK if I send a non RFC
> > > > version or shall we wait for couple of days more ?
> > >
> > > I guess I'd like non-RFC version of patches 1-22 in a series. I
> > > believe it makes sense to add 30, 32, 49, 50 to them, as they are
> > > simple and fix a bug.
> > >
> > > Would that work for you?
> > >
> > Sure ill get on posting the above mentioned patches as non-RFC in a series.
> >
> > How do we tackle with rest of the patches ?
> 
> Well... I applied this batch. If someone can explain the mutex
> vs. spinlock thing, then I guess we can do next batch up to 35...
> 
Thank you for queuing in the patches.

I have replied on patch 24/50 to add my two cents.

> OTOH I did not go through those patches in detail, and RFC is good
> enough for review, so... maybe you can just wait.
> 
Sure will wait.

Cheers,
Prabhakar

> Best regards,
>     	     	    	   	    	   	      	    Pavel
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex
  2020-10-20 21:56     ` Lad Prabhakar
@ 2020-10-21 18:34       ` Pavel Machek
  0 siblings, 0 replies; 73+ messages in thread
From: Pavel Machek @ 2020-10-21 18:34 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1683 bytes --]

Hi!

> > > commit 3d3248dbd018502f654064c78efcd2e165ab3486 upstream.
> > >
> > > The pci_epc_ops is not intended to be invoked from interrupt context.
> > > Hence replace spin_lock_irqsave and spin_unlock_irqrestore with
> > > mutex_lock and mutex_unlock respectively.
> > 
> > Could I get some kind of explanation why this is good idea?
> > 
> Apart of one mentioned above other point I would add is on a single core machine mutex_lock/unlock would be good choice.
> 
> Also to add the callbacks in controller driver might sleep. For example in raise_irq callback  [1], [2].
> 
> > As long as code protected by the locks does not sleep, spinlocks are
> > okay... (but they should not need "_irqsave" variants).
> > 
> > They are likely to have better performance, too, when protected code
> > is small and fast.
> > 
> I do agree with the above two points *if the code isn't sleeping*.

Okay, we can't really protect sleeping code with a mutex.

> [1] https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/drivers/pci/controller/pcie-rockchip-ep.c?h=linux-4.19.y-cip#n410

But this one is not sleeping. It is mdelay(), not msleep().

> [2] https://git.kernel.org/pub/scm/linux/kernel/git/cip/linux-cip.git/tree/drivers/pci/controller/pcie-cadence-ep.c?h=linux-4.19.y-cip#n310

And same here.

If there's a place which does sleep with the spinlock held, I'd still
be curious.

OTOH, 1 msec is already threshold where mutex makes sense, so... this
is okay.

Thanks,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion Lad Prabhakar
@ 2020-10-21 19:00   ` Pavel Machek
  2020-10-21 20:16     ` Lad Prabhakar
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-21 19:00 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1141 bytes --]

Hi!

> From: Vidya Sagar <vidyas@nvidia.com>
> 
> commit 0ef22dcf0c1871888c4c0ee46a9d9c494f2fe997 upstream.
> 
> Add support to send notifications to EPF from EPC once the core
> registers initialization is complete.

>  
> +/**
> + * pci_epc_init_notify() - Notify the EPF device that EPC device's core
> + *			   initialization is completed.
> + * @epc: the EPC device whose core initialization is completeds
> + *
> + * Invoke to Notify the EPF device that the EPC device's initialization
> + * is completed.
> + */
> +void pci_epc_init_notify(struct pci_epc *epc)
> +{
> +	if (!epc || IS_ERR(epc))
> +		return;
> +
> +	atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL);
> +}
> +EXPORT_SYMBOL_GPL(pci_epc_init_notify);

Is this used somewhere? This adds symbol but noone calls this, and
AFAICT it is not used in the rest of the series, either.

We can merge it, anyway, I guess, but... explanation would be welcome.

Best regards,
								Pavel

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
  2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file Lad Prabhakar
@ 2020-10-21 19:06   ` Pavel Machek
  2020-10-21 20:28     ` Lad Prabhakar
  0 siblings, 1 reply; 73+ messages in thread
From: Pavel Machek @ 2020-10-21 19:06 UTC (permalink / raw)
  To: Lad Prabhakar; +Cc: cip-dev, Nobuhiro Iwamatsu, Pavel Machek, Biju Das

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Hi!

> commit 78a0d7f2f5a31357bce68012d886507b4cf33598 upstream.
> 
> Move shareable code to common file pcie-rcar.c and the #defines to
> pcie-rcar.h so that the common code can be reused with endpoint driver.
> There are no functional changes with this patch for the host controller
> driver.

Whoa.

So... original patch _moved_ shared code to new place.

This version creates another copy of shared code, probably subtly
different from the other one.

Is that good idea? Won't two copies cause problems depending on
.config? Could we share code, as the mainline does?

Anyway, patches up to previous one -- [37/50] arm64: defconfig: Enable
CONFIG_PCIE_RCAR_HOST look okay to me, so if you can send them as
non-RFC version, I cal likely apply them.

Best regards,
								Pavel

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion
  2020-10-21 19:00   ` Pavel Machek
@ 2020-10-21 20:16     ` Lad Prabhakar
  0 siblings, 0 replies; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-21 20:16 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 1818 bytes --]

Hi Pavel,

Thank you for the review.

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 21 October 2020 20:01
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion
> 
> Hi!
> 
> > From: Vidya Sagar <vidyas@nvidia.com>
> >
> > commit 0ef22dcf0c1871888c4c0ee46a9d9c494f2fe997 upstream.
> >
> > Add support to send notifications to EPF from EPC once the core
> > registers initialization is complete.
> 
> >
> > +/**
> > + * pci_epc_init_notify() - Notify the EPF device that EPC device's core
> > + *			   initialization is completed.
> > + * @epc: the EPC device whose core initialization is completeds
> > + *
> > + * Invoke to Notify the EPF device that the EPC device's initialization
> > + * is completed.
> > + */
> > +void pci_epc_init_notify(struct pci_epc *epc)
> > +{
> > +	if (!epc || IS_ERR(epc))
> > +		return;
> > +
> > +	atomic_notifier_call_chain(&epc->notifier, CORE_INIT, NULL);
> > +}
> > +EXPORT_SYMBOL_GPL(pci_epc_init_notify);
> 
> Is this used somewhere? This adds symbol but noone calls this, and
> AFAICT it is not used in the rest of the series, either.
> 
Yep none users (only dwc uses it mainline).

> We can merge it, anyway, I guess, but... explanation would be welcome.
>
Ill post it as part of non-RFC feel free to drop it.

Cheers,
Prabhakar
 
> Best regards,
> 								Pavel
> 
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
  2020-10-21 19:06   ` Pavel Machek
@ 2020-10-21 20:28     ` Lad Prabhakar
  2020-10-22 19:42       ` Pavel Machek
  0 siblings, 1 reply; 73+ messages in thread
From: Lad Prabhakar @ 2020-10-21 20:28 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das


[-- Attachment #1: Type: text/plain, Size: 1926 bytes --]

Hi Pavel,

Thank you for the review.

> -----Original Message-----
> From: Pavel Machek <pavel@denx.de>
> Sent: 21 October 2020 20:07
> To: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Cc: cip-dev@lists.cip-project.org; Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek <pavel@denx.de>; Biju Das
> <biju.das.jz@bp.renesas.com>
> Subject: Re: [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
> 
> Hi!
> 
> > commit 78a0d7f2f5a31357bce68012d886507b4cf33598 upstream.
> >
> > Move shareable code to common file pcie-rcar.c and the #defines to
> > pcie-rcar.h so that the common code can be reused with endpoint driver.
> > There are no functional changes with this patch for the host controller
> > driver.
> 
> Whoa.
> 
> So... original patch _moved_ shared code to new place.
> 
> This version creates another copy of shared code, probably subtly
> different from the other one.
> 
> Is that good idea? Won't two copies cause problems depending on
> .config? Could we share code, as the mainline does?
> 
My main concern was this produces a big diff which would make it difficult for review. And CONFIG_PCIE_RCAR_HOST by default selects CONFIG_PCIE_RCAR which builds the host driver.
pcie-rcar.c is the same as mainline only that pcie-rcar-host.c is untouched here.

If you are OK ill post the similar changes to pcie-rcar-host.c as done in the actual upstream patch.

> Anyway, patches up to previous one -- [37/50] arm64: defconfig: Enable
> CONFIG_PCIE_RCAR_HOST look okay to me, so if you can send them as
> non-RFC version, I cal likely apply them.
> 
I shall get on posting the 2nd bunch of non-RFC.

Cheers,
Prabhakar

> Best regards,
> 								Pavel
> 
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support
  2020-10-15 18:01       ` Pavel Machek
@ 2020-10-22 18:23         ` Pavel Machek
  0 siblings, 0 replies; 73+ messages in thread
From: Pavel Machek @ 2020-10-22 18:23 UTC (permalink / raw)
  To: Pavel Machek; +Cc: cip-dev, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 578 bytes --]

On Thu 2020-10-15 20:01:15, Pavel Machek wrote:
> Hi!
> 
> > > Plain 0 would be enough
> > >
> > Agreed.
> > 
> > Ill post patches upstream to fix this and then backport or do you
> >want me to do the changes in place ?
> 
> Yes, thank you.

I mean "fix it upstream first" is good strategy here. This is just
cosmetics. You don't even have to backport it.. just fix it upstream.


Best regards,
								Pavel


-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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* Re: [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file
  2020-10-21 20:28     ` Lad Prabhakar
@ 2020-10-22 19:42       ` Pavel Machek
  0 siblings, 0 replies; 73+ messages in thread
From: Pavel Machek @ 2020-10-22 19:42 UTC (permalink / raw)
  To: cip-dev; +Cc: Pavel Machek, Nobuhiro Iwamatsu, Biju Das

[-- Attachment #1.1: Type: text/plain, Size: 1658 bytes --]

Hi!

> > > commit 78a0d7f2f5a31357bce68012d886507b4cf33598 upstream.
> > >
> > > Move shareable code to common file pcie-rcar.c and the #defines to
> > > pcie-rcar.h so that the common code can be reused with endpoint driver.
> > > There are no functional changes with this patch for the host controller
> > > driver.
> > 
> > Whoa.
> > 
> > So... original patch _moved_ shared code to new place.
> > 
> > This version creates another copy of shared code, probably subtly
> > different from the other one.
> > 
> > Is that good idea? Won't two copies cause problems depending on
> > .config? Could we share code, as the mainline does?
> > 
> My main concern was this produces a big diff which would make it difficult for review. And CONFIG_PCIE_RCAR_HOST by default selects CONFIG_PCIE_RCAR which builds the host driver.
> pcie-rcar.c is the same as mainline only that pcie-rcar-host.c is untouched here.
> 
> If you are OK ill post the similar changes to pcie-rcar-host.c as done in the actual upstream patch.
>

I'm not 100% sure what you are proposing, but let's do that. We should
not end with two copies of the identical code in -cip, right?

> > Anyway, patches up to previous one -- [37/50] arm64: defconfig: Enable
> > CONFIG_PCIE_RCAR_HOST look okay to me, so if you can send them as
> > non-RFC version, I cal likely apply them.
> > 
> I shall get on posting the 2nd bunch of non-RFC.

I believe we are ready for rest of the patches.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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^ permalink raw reply	[flat|nested] 73+ messages in thread

end of thread, back to index

Thread overview: 73+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-12 14:18 [cip-dev] [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 01/50] PCI: endpoint: Add new pci_epc_ops to get EPC features Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 02/50] PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 03/50] PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 04/50] PCI: pci-dra7xx: " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 05/50] PCI: rockchip: " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 06/50] PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 07/50] PCI: endpoint: Add helper to get first unreserved BAR Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 08/50] PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 09/50] PCI: pci-epf-test: Remove setting epf_bar flags in function driver Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 10/50] PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 11/50] PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 12/50] PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 13/50] PCI: rockchip: Remove pci_epf_linkup() from Rockchip " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 14/50] PCI: designware-plat: Remove setting epc->features in Designware plat " Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 15/50] PCI: endpoint: Remove features member in struct pci_epc Lad Prabhakar
2020-10-12 14:18 ` [cip-dev] [RFC PATCH 4.19.y-cip 16/50] PCI: endpoint: Fix a potential NULL pointer dereference Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 17/50] PCI: endpoint: Add support to specify alignment for buffers allocated to BARs Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 18/50] PCI: endpoint: Set endpoint controller pointer to NULL Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 19/50] PCI: endpoint: Allocate enough space for fixed size BAR Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 20/50] PCI: endpoint: Skip odd BAR when skipping 64bit BAR Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 21/50] PCI: endpoint: Clear BAR before freeing its space Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 22/50] PCI: endpoint: Cast the page number to phys_addr_t Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 23/50] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 24/50] PCI: endpoint: Replace spinlock with mutex Lad Prabhakar
2020-10-20 20:43   ` Pavel Machek
2020-10-20 21:56     ` Lad Prabhakar
2020-10-21 18:34       ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 25/50] PCI: endpoint: Protect concurrent access to pci_epf_ops " Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 26/50] PCI: endpoint: Assign function number for each PF in EPC core Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 27/50] PCI: endpoint: Add core init notifying feature Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 28/50] PCI: endpoint: Add notification for core init completion Lad Prabhakar
2020-10-21 19:00   ` Pavel Machek
2020-10-21 20:16     ` Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 29/50] PCI: pci-epf-test: Add support to defer core initialization Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 30/50] PCI: endpoint: Fix clearing start entry in configfs Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 31/50] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 32/50] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 33/50] PCI: endpoint: Pass page size as argument to pci_epc_mem_init() Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 34/50] PCI: endpoint: Add support to handle multiple base for mapping outbound memory Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 35/50] PCI: endpoint: functions/pci-epf-test: Print throughput information Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 36/50] PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 37/50] arm64: defconfig: Enable CONFIG_PCIE_RCAR_HOST Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 38/50] PCI: rcar: Move shareable code to a common file Lad Prabhakar
2020-10-21 19:06   ` Pavel Machek
2020-10-21 20:28     ` Lad Prabhakar
2020-10-22 19:42       ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 39/50] PCI: rcar: Fix calculating mask for PCIEPAMR register Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 40/50] dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 41/50] PCI: rcar: Add endpoint mode support Lad Prabhakar
2020-10-14  9:22   ` Pavel Machek
2020-10-15 16:31     ` Lad Prabhakar
2020-10-15 18:01       ` Pavel Machek
2020-10-22 18:23         ` Pavel Machek
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 42/50] arm64: defconfig: Enable R-Car PCIe endpoint driver Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 43/50] dt-bindings: pci: rcar-pci-ep: Document r8a774a1 and r8a774b1 Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 44/50] arm64: dts: renesas: r8a774c0: Add PCIe EP node Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 45/50] arm64: dts: renesas: r8a774a1: Add PCIe EP nodes Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 46/50] arm64: dts: renesas: r8a774b1: " Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 47/50] misc: pci_endpoint_test: Add Device ID for RZ/G2E PCIe controller Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 48/50] misc: pci_endpoint_test: Add Device ID for RZ/G2M and RZ/G2N PCIe controllers Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 49/50] tools: PCI: Exit with error code when test fails Lad Prabhakar
2020-10-12 14:19 ` [cip-dev] [RFC PATCH 4.19.y-cip 50/50] tools: PCI: Fix fd leakage Lad Prabhakar
2020-10-14  9:39 ` [cip-dev] If you are using PCIe EP, speak up was Re: [RFC PATCH 4.19.y-cip 00/50] Add PCIe EP support for Renesas R-Car Gen3 and RZ/G2x Pavel Machek
2020-10-15 16:18   ` Lad Prabhakar
2020-10-20  7:16   ` Lad Prabhakar
2020-10-20 10:34     ` Pavel Machek
2020-10-20 12:01     ` Pavel Machek
2020-10-20 13:01       ` Lad Prabhakar
2020-10-20 20:48         ` Pavel Machek
2020-10-20 21:58           ` Lad Prabhakar
2020-10-14 10:07 ` [cip-dev] " Pavel Machek
2020-10-15 16:27   ` Lad Prabhakar

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