From: Nicolin Chen <Guangyu.Chen@freescale.com>
To: broonie@kernel.org
Cc: tiwai@suse.de, alsa-devel@alsa-project.org, lgirdwood@gmail.com
Subject: [PATCH RESEND 0/4] ASoC: fsl_esai: Fix some issues
Date: Tue, 6 May 2014 16:55:58 +0800 [thread overview]
Message-ID: <cover.1399366227.git.Guangyu.Chen@freescale.com> (raw)
Sorry for this resend. I just found my previous patches have
not been delivered successfully to the alsa maillist.
This series of patches fix the following problems:
PATCH-1 for an incorrect ratio range check.
PATCH-2 for an incorrect bypass settings of FSYS clock source.
PATCH-3 for duplicated calculations and configurations of dividers
PATCH-4 for mismatched init flow of configuration comparing to RM.
Nicolin Chen (4):
ASoC: fsl_esai: Fix incorrect condition within ratio range check for
FP
ASoC: fsl_esai: Only bypass sck_div for EXTAL source
ASoC: fsl_esai: Bypass divider settings if clock requirement is not
changed
ASoC: fsl_esai: Set PCRC and PRRC registers at the end of hw_params()
sound/soc/fsl/fsl_esai.c | 45 ++++++++++++++++++++++++++++++++++-----------
1 file changed, 34 insertions(+), 11 deletions(-)
--
1.8.4
next reply other threads:[~2014-05-06 8:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-06 8:55 Nicolin Chen [this message]
2014-05-06 8:55 ` [PATCH RESEND 1/4] ASoC: fsl_esai: Fix incorrect condition within ratio range check for FP Nicolin Chen
2014-05-06 8:56 ` [PATCH RESEND 2/4] ASoC: fsl_esai: Only bypass sck_div for EXTAL source Nicolin Chen
2014-05-06 8:56 ` [PATCH RESEND 3/4] ASoC: fsl_esai: Bypass divider settings if clock requirement is not changed Nicolin Chen
2014-05-06 8:56 ` [PATCH RESEND 4/4] ASoC: fsl_esai: Set PCRC and PRRC registers at the end of hw_params() Nicolin Chen
2014-05-12 22:15 ` [PATCH RESEND 0/4] ASoC: fsl_esai: Fix some issues Mark Brown
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