Re: [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers

From: "Sripada, Radhakrishna" <radhakrishna.sripada@intel.com>
To: "intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"Souza, Jose" <jose.souza@intel.com>
Subject: Re: [PATCH v6] drm/i915/icl: Fix clockgating issue when using scalers
Date: Thu, 11 Apr 2019 23:29:21 +0000	[thread overview]
Message-ID: <d316786ed9265b8f46066b4b57a33fd61a7a61cf.camel@intel.com> (raw)
In-Reply-To: <db99ad73ff89407d6985896dd5715d356b1674d9.camel@intel.com>

On Thu, 2019-04-11 at 14:41 -0700, Souza, Jose wrote:
> On Fri, 2019-04-05 at 14:14 -0700, Radhakrishna Sripada wrote:
> > Fixes the clock-gating issue when pipe scaling is enabled.
> > (Lineage #2006604312)
> > 
> > V2: Fix typo in headline(Chris)
> >     Handle the non double buffered nature of the register(Ville)
> > V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks
> > unrelated.
> > V4: Split the icl and skl wa's(Ville)
> > V5: Split the checks for icl and skl(Ville)
> > V6: Correct the flipped checks in intel_pre_plane_update(Ville)
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: Aditya Swarup <aditya.swarup@intel.com>
> > Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com
> > >
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 39 ++++++++++++++++++++++++
> > ----
> >  1 file changed, 34 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index cf6046390eeb..ab820cad990d 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -466,6 +466,7 @@ static const struct intel_limit
> > intel_limits_bxt
> > = {
> >  	.p2 = { .p2_slow = 1, .p2_fast = 20 },
> >  };
> >  
> > +/* WA Display #0827: Gen9:all */
> >  static void
> >  skl_wa_827(struct drm_i915_private *dev_priv, int pipe, bool
> > enable)
> >  {
> > @@ -479,6 +480,18 @@ skl_wa_827(struct drm_i915_private *dev_priv,
> > int pipe, bool enable)
> >  			   ~(DUPS1_GATING_DIS | DUPS2_GATING_DIS));
> >  }
> >  
> > +/* Wa_2006604312:icl */
> > +static void
> > +icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, int
> > pipe,
> > bool enable)
> > +{
> > +	if (enable)
> > +		I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > +			   I915_READ(CLKGATE_DIS_PSL(pipe)) |
> > DPFR_GATING_DIS);
> > +	else
> > +		I915_WRITE(CLKGATE_DIS_PSL(pipe),
> > +			   I915_READ(CLKGATE_DIS_PSL(pipe)) &
> > ~DPFR_GATING_DIS);
> > +}
> > +
> >  static bool
> >  needs_modeset(const struct drm_crtc_state *state)
> >  {
> > @@ -5495,6 +5508,16 @@ static bool needs_nv12_wa(struct
> > drm_i915_private *dev_priv,
> >  	return false;
> >  }
> >  
> > +static bool needs_scalerclk_wa(struct drm_i915_private *dev_priv,
> > +			       const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	/* Wa_2006604312:icl */
> > +	if (crtc_state->pch_pfit.enabled && IS_ICELAKE(dev_priv))
> > +		return true;
> 
> Looking to BSpec this WA is needed for other platforms too like
> elkhartlake, so I would change to:
> 
> if (INTEL_GEN(dev_priv) >= 11)
> 	return crtc_state->pch_pfit.enabled;
That is an interesting feedback. When multiple platforms are involved I
would rather track it as seperate patches for downstream
maintainability and restrict the usage to (IS_ICELAKE(dev_priv) |
IS_ELKHARTLAKE(dev_priv)) comapred to using (INTEL_GEN(dev_priv) >= 11)
IMO that needs to be carried out in a seperate patch. Thoughts?

- Radhakrishna(RK) Sripada
> 
> > +
> > +	return false;
> > +}
> > +
> >  static void intel_post_plane_update(struct intel_crtc_state
> > *old_crtc_state)
> >  {
> >  	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state-
> > > base.crtc);
> > 
> > @@ -5528,11 +5551,13 @@ static void intel_post_plane_update(struct
> > intel_crtc_state *old_crtc_state)
> >  			intel_post_enable_primary(&crtc->base,
> > pipe_config);
> >  	}
> >  
> > -	/* Display WA 827 */
> >  	if (needs_nv12_wa(dev_priv, old_crtc_state) &&
> > -	    !needs_nv12_wa(dev_priv, pipe_config)) {
> > +	    !needs_nv12_wa(dev_priv, pipe_config))
> >  		skl_wa_827(dev_priv, crtc->pipe, false);
> > -	}
> > +
> > +	if (needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> > +	    !needs_scalerclk_wa(dev_priv, pipe_config))
> > +		icl_wa_scalerclkgating(dev_priv, crtc->pipe, false);
> >  }
> >  
> >  static void intel_pre_plane_update(struct intel_crtc_state
> > *old_crtc_state,
> > @@ -5569,9 +5594,13 @@ static void intel_pre_plane_update(struct
> > intel_crtc_state *old_crtc_state,
> >  
> >  	/* Display WA 827 */
> >  	if (!needs_nv12_wa(dev_priv, old_crtc_state) &&
> > -	    needs_nv12_wa(dev_priv, pipe_config)) {
> > +	    needs_nv12_wa(dev_priv, pipe_config))
> >  		skl_wa_827(dev_priv, crtc->pipe, true);
> > -	}
> > +
> > +	/* Wa_2006604312:icl */
> > +	if (!needs_scalerclk_wa(dev_priv, old_crtc_state) &&
> > +	    needs_scalerclk_wa(dev_priv, pipe_config))
> > +		icl_wa_scalerclkgating(dev_priv, crtc->pipe, true);
> >  
> >  	/*
> >  	 * Vblank time updates from the shadow to live plane control
> > register
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