Re: [PATCH v2 1/9] arm64: perf: avoid PMXEV* indirection

From: Julien Thierry <julien.thierry@arm.com>
To: "liwei (GF)" <liwei391@huawei.com>, linux-arm-kernel@lists.infradead.org
Cc: mark.rutland@arm.com, peterz@infradead.org,
	Catalin Marinas <catalin.marinas@arm.com>,
	will.deacon@arm.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, mingo@redhat.com,
	libin 00196512 <huawei.libin@huawei.com>,
	guohanjun 00470146 <guohanjun@huawei.com>,
	namhyung@kernel.org, jolsa@redhat.com
Subject: Re: [PATCH v2 1/9] arm64: perf: avoid PMXEV* indirection
Date: Mon, 25 Mar 2019 13:59:51 +0000	[thread overview]
Message-ID: <d81ffdb7-3815-d47d-11a4-ee3b7e285850@arm.com> (raw)
In-Reply-To: <727231d0-1a41-a7ea-3834-518b7d5b802b@huawei.com>

Hi

On 25/03/2019 12:37, liwei (GF) wrote:
> When PMSELR_EL0.SEL == 31, the register PMXEVTYPER_EL0 accesses PMCCFILTR_EL0.
> I think we need to add a branch to process such condition.
> 
> Signed-off-by: Wei Li <liwei391@huawei.com>
> ---
>  arch/arm64/kernel/perf_event.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
> index 42fe7109468f..76bc55e67137 100644
> --- a/arch/arm64/kernel/perf_event.c
> +++ b/arch/arm64/kernel/perf_event.c
> @@ -538,7 +538,7 @@ static inline bool armv8pmu_event_is_chained(struct perf_event *event)
>  		PMEVN_CASE(28, case_macro);			\
>  		PMEVN_CASE(29, case_macro);			\
>  		PMEVN_CASE(30, case_macro);			\
> -		default: WARN(1, "Inavlid PMEV* index");	\
> +		default: WARN(1, "Inavlid PMEV* index %#x", __x);	\

I'm not convinced we need that. We're generating register accesses. If
we try to access a register that doesn't exist, the compiler/assembler
will complain and fail to build. So that default case would not be run.

Thanks,

Julien

>  		}						\
>  	} while (0)
>  
> @@ -684,7 +684,7 @@ static inline void armv8pmu_write_evtype(int idx, u32 val)
>  	write_pmevtypern(counter, val);
>  }
>  
> -static inline void armv8pmu_write_event_type(struct perf_event *event)
> +static inline void armv8pmu_write_hw_type(struct perf_event *event)
>  {
>  	struct hw_perf_event *hwc = &event->hw;
>  	int idx = hwc->idx;
> @@ -705,6 +705,21 @@ static inline void armv8pmu_write_event_type(struct perf_event *event)
>  	}
>  }
>  
> +static inline void armv8pmu_write_event_type(struct perf_event *event)
> +{
> +	struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
> +	struct hw_perf_event *hwc = &event->hw;
> +	int idx = hwc->idx;
> +
> +	if (!armv8pmu_counter_valid(cpu_pmu, idx))
> +		pr_err("CPU%u reading wrong counter %d\n",
> +			smp_processor_id(), idx);
> +	else if (idx == ARMV8_IDX_CYCLE_COUNTER)
> +		write_sysreg(hwc->config_base & ARMV8_PMU_EVTYPE_MASK, pmccfiltr_el0);
> +	else
> +		armv8pmu_write_hw_type(event);
> +}
> +
>  static inline int armv8pmu_enable_counter(int idx)
>  {
>  	u32 counter = ARMV8_IDX_TO_COUNTER(idx);
> 

-- 
Julien Thierry

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