From: Joseph Lo <josephl@nvidia.com>
To: <linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH V3 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210
Date: Wed, 19 Dec 2018 15:08:40 +0800 [thread overview]
Message-ID: <df7945b1-cbf2-e7bd-fce0-8fdb24f1f7d2@nvidia.com> (raw)
In-Reply-To: <154515602466.238328.7202899555618997431@swboyd.mtv.corp.google.com>
On 12/19/18 2:00 AM, Stephen Boyd wrote:
> Quoting Joseph Lo (2018-12-18 01:12:22)
>> diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
>> index 7ddacae5d0b1..57902ab43f4a 100644
>> --- a/drivers/clk/tegra/Kconfig
>> +++ b/drivers/clk/tegra/Kconfig
>> @@ -5,3 +5,8 @@ config TEGRA_CLK_EMC
>> config CLK_TEGRA_BPMP
>> def_bool y
>> depends on TEGRA_BPMP
>> +
>> +config TEGRA_CLK_DFLL
>> + depends on (ARCH_TEGRA_124_SOC || ARCH_TEGRA_210_SOC)
>
> Nitpick: Drop the parenthesis please.
Hi Stephen,
Thanks for reviewing. Will fix that.
Joseph
>
>> + select PM_OPP
>> + def_bool y
>
>
>
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next prev parent reply other threads:[~2018-12-19 7:09 UTC|newest]
Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-18 9:12 [PATCH V3 00/20] Tegra210 DFLL support Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 01/20] dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:56 ` Jon Hunter
2018-12-18 9:56 ` Jon Hunter
2018-12-18 9:56 ` Jon Hunter
2018-12-18 15:19 ` Rob Herring
2018-12-18 15:19 ` Rob Herring
2018-12-18 15:19 ` Rob Herring
2018-12-19 7:04 ` Joseph Lo
2018-12-19 7:04 ` Joseph Lo
2018-12-19 7:04 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 02/20] dt-bindings: clock: tegra124-dfll: add Tegra210 support Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 15:44 ` Rob Herring
2018-12-18 15:44 ` Rob Herring
2018-12-18 15:44 ` Rob Herring
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 03/20] dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 15:45 ` Rob Herring
2018-12-18 15:45 ` Rob Herring
2018-12-18 15:45 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 04/20] dt-bindings: cpufreq: tegra124: remove cpu_lp clock " Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 15:47 ` Rob Herring
2018-12-18 15:47 ` Rob Herring
2018-12-18 15:47 ` Rob Herring
2018-12-18 9:12 ` [PATCH V3 05/20] clk: tegra: dfll: registration for multiple SoCs Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 06/20] clk: tegra: dfll: CVB calculation alignment with the regulator Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:58 ` Jon Hunter
2018-12-18 9:58 ` Jon Hunter
2018-12-18 9:58 ` Jon Hunter
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 18:02 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 07/20] clk: tegra: dfll: support PWM regulator control Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 10:00 ` Jon Hunter
2018-12-18 10:00 ` Jon Hunter
2018-12-18 10:00 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 08/20] clk: tegra: dfll: round down voltages based on alignment Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 10:05 ` Jon Hunter
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 18:41 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 09/20] clk: tegra: dfll: add CVB tables for Tegra210 Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 10:05 ` Jon Hunter
2018-12-18 10:05 ` Jon Hunter
2018-12-18 10:05 ` Jon Hunter
2018-12-18 18:42 ` Stephen Boyd
2018-12-18 18:42 ` Stephen Boyd
2018-12-18 18:42 ` Stephen Boyd
2018-12-18 9:12 ` [PATCH V3 10/20] clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 18:00 ` Stephen Boyd
2018-12-18 18:00 ` Stephen Boyd
2018-12-18 18:00 ` Stephen Boyd
2018-12-19 7:08 ` Joseph Lo [this message]
2018-12-18 9:12 ` [PATCH V3 11/20] cpufreq: tegra124: do not handle the CPU rail Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:37 ` Rafael J. Wysocki
2018-12-18 9:37 ` Rafael J. Wysocki
2018-12-18 9:37 ` Rafael J. Wysocki
2018-12-19 6:24 ` Joseph Lo
2018-12-19 6:24 ` Joseph Lo
2018-12-19 6:24 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 12/20] cpufreq: tegra124: extend to support Tegra210 Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 13/20] cpufreq: dt-platdev: add Tegra210 to blacklist Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 14/20] arm64: dts: tegra210: add DFLL clock Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 15/20] arm64: dts: tegra210: add CPU clocks Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 16/20] arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 17/20] arm64: dts: tegra210-p2371-2180: enable DFLL clock Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 18/20] arm64: dts: tegra210-smaug: add CPU power rail regulator Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 19/20] arm64: dts: tegra210-smaug: enable DFLL clock Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` [PATCH V3 20/20] arm64: defconfig: Enable MAX8973 regulator Joseph Lo
2018-12-18 9:12 ` Joseph Lo
2018-12-18 9:12 ` Joseph Lo
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