From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
To: vkoul@kernel.org, dan.j.williams@intel.com,
michal.simek@xilinx.com, nick.graumann@gmail.com,
andrea.merello@gmail.com, appana.durga.rao@xilinx.com,
mcgrof@kernel.org
Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Subject: [PATCH -next 2/4] dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_config
Date: Thu, 26 Sep 2019 16:20:58 +0530 [thread overview]
Message-ID: <1569495060-18117-3-git-send-email-radhey.shyam.pandey@xilinx.com> (raw)
In-Reply-To: <1569495060-18117-1-git-send-email-radhey.shyam.pandey@xilinx.com>
In vdma_channel_set_config clear the delay, frame count and master mask
before updating their new values. It avoids programming incorrect state
when input parameters are different from default.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 1fbe025..5d56f1e 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -68,6 +68,9 @@
#define XILINX_DMA_DMACR_CIRC_EN BIT(1)
#define XILINX_DMA_DMACR_RUNSTOP BIT(0)
#define XILINX_DMA_DMACR_FSYNCSRC_MASK GENMASK(6, 5)
+#define XILINX_DMA_DMACR_DELAY_MASK GENMASK(31, 24)
+#define XILINX_DMA_DMACR_FRAME_COUNT_MASK GENMASK(23, 16)
+#define XILINX_DMA_DMACR_MASTER_MASK GENMASK(11, 8)
#define XILINX_DMA_REG_DMASR 0x0004
#define XILINX_DMA_DMASR_EOL_LATE_ERR BIT(15)
@@ -2118,8 +2121,10 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
chan->config.gen_lock = cfg->gen_lock;
chan->config.master = cfg->master;
+ dmacr &= ~XILINX_DMA_DMACR_GENLOCK_EN;
if (cfg->gen_lock && chan->genlock) {
dmacr |= XILINX_DMA_DMACR_GENLOCK_EN;
+ dmacr &= ~XILINX_DMA_DMACR_MASTER_MASK;
dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT;
}
@@ -2135,11 +2140,13 @@ int xilinx_vdma_channel_set_config(struct dma_chan *dchan,
chan->config.delay = cfg->delay;
if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) {
+ dmacr &= ~XILINX_DMA_DMACR_FRAME_COUNT_MASK;
dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT;
chan->config.coalesc = cfg->coalesc;
}
if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) {
+ dmacr &= ~XILINX_DMA_DMACR_DELAY_MASK;
dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT;
chan->config.delay = cfg->delay;
}
--
1.7.1
next prev parent reply other threads:[~2019-09-26 10:51 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-26 10:50 [PATCH -next 0/4] dmaengine: xilinx_dma: Minor functional fixes Radhey Shyam Pandey
2019-09-26 10:50 ` [PATCH -next 1/4] dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transfer Radhey Shyam Pandey
2019-09-26 10:50 ` Radhey Shyam Pandey [this message]
2019-09-26 10:50 ` [PATCH -next 3/4] dmaengine: xilinx_dma: use devm_platform_ioremap_resource() Radhey Shyam Pandey
2019-09-26 10:51 ` [PATCH -next 4/4] dmaengine: xilinx_dma: Remove clk_get error message for probe defer Radhey Shyam Pandey
2019-10-15 10:12 ` [PATCH -next 0/4] dmaengine: xilinx_dma: Minor functional fixes Vinod Koul
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