[PATCH -next 0/6] dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support

[Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>]

This patchset adds Xilinx AXI MCDMA IP support. The AXI MCDMA provides
high-bandwidth direct memory access between memory and AXI4-Stream target
peripherals. It supports up to 16 independent read/write channels.

MCDMA IP supports per channel interrupt output but driver support one
interrupt per channel for simplification. IP specification/programming
sequence and register description is mentioned in PG [1].

The driver is tested with xilinx internal dmatest client. In end usecase
MCDMA will be used by xilinx axiethernet driver using dma API's.

Changes since RFC[2]:
- Remove xilinx axidma multichannel support.
- Addressed all RFC comments except modularizing initialization of channel
  segment is skipped as it would create tight coupling b/w axidma and
  mcdma internal structures.
- Include MCDMA IP description in Kconfig.
- Few regression fixes from xilinx tree.

NOTE: This patchset is based on next and previous[3] axidma series.

[1] https://www.xilinx.com/support/documentation/ip_documentation/axi_mcdma/v1_0/pg288-axi-mcdma.pdf
[2] https://spinics.net/lists/devicetree/msg242427.html
[3] https://www.spinics.net/lists/dmaengine/msg19910.html

Radhey Shyam Pandey (6):
  dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support
  dt-bindings: dmaengine: xilinx_dma: Fix formatting and style
  dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
  dmaengine: xilinx_dma: Remove axidma multichannel mode support
  dmaengine: xilinx_dma: Extend dma_config struct to store irq routine
    handle
  dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support

 .../devicetree/bindings/dma/xilinx/xilinx_dma.txt  |  24 +-
 drivers/dma/Kconfig                                |   4 +
 drivers/dma/xilinx/xilinx_dma.c                    | 517 ++++++++++++++++-----
 3 files changed, 431 insertions(+), 114 deletions(-)

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2.7.4