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Tue, 22 Oct 2019 10:00:34 -0700 Received: from xsj-pvapsmtp01 (smtp-fallback.xilinx.com [149.199.38.66] (may be forged)) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0WZR030509; Tue, 22 Oct 2019 10:00:32 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059Z-I4; Tue, 22 Oct 2019 10:00:31 -0700 Received: by ubuntu (Postfix, from userid 13245) id C26F510112A; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 1/6] dt-bindings: dmaengine: xilinx_dma: Remove axidma multichannel support Date: Tue, 22 Oct 2019 22:30:17 +0530 Message-Id: <1571763622-29281-2-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--2.613-7.0-31-1 X-imss-scan-details: No--2.613-7.0-31-1;No--2.613-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(396003)(346002)(136003)(376002)(189003)(199004)(107886003)(26005)(76176011)(51416003)(6266002)(14444005)(7416002)(305945005)(48376002)(2906002)(4326008)(5660300002)(36756003)(81156014)(8936002)(81166006)(50466002)(8676002)(50226002)(47776003)(106002)(42186006)(446003)(336012)(6666004)(356004)(478600001)(70586007)(186003)(11346002)(486006)(126002)(476003)(2616005)(426003)(16586007)(103686004)(70206006)(316002)(921003)(42866002)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:DM6PR02MB6377;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: fd846e4f-937c-4dbb-6047-08d757115e96 X-MS-TrafficTypeDiagnostic: DM6PR02MB6377: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7219; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: F5n63usNrYXjfAqdchaP2QBSPHqe+G4x+0YS1YfQbJj8rGwu62csBi0J0+/TcVLRMtMq1sYdVoH6O0muy0g0XG0RfHTnK5YfE3gSaHa7r8qN4ndTwCNbvfTLSvYX3OpEgMK7u2+g2ZcbTkMYQtMl9tl/nhb8ymtkYfDCiO9LQvmBW9hasiI4jTel3YV6Tt4Nmyv0dlRMWZv3VXulw/Bi5woXn4ME1rB7Bo4uyr5BaKkOZYIFAcD1Qdqzm7pmspul7moOFPCtMCptSqjBu+YbJu0queJS9oYlNLgwmnQihJzC/IX+X5m9kF5YSRGmoOp04Mhqt/HPIwSxDcuADt0ewO4eam2AqlOyRrPj0+OtU06H5wC7UPv2lVDukmXF8ofgg0BMN1rhOuqfvA68eksCHo+zwVyrJxhetNw9Mmpg6O7kv/quP3BDbg/2oFDwEawk X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:40.7757 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd846e4f-937c-4dbb-6047-08d757115e96 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6377 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver(added in the subsequent commits). Inline with it remove axidma multichannel optional properties i.e xlnx,mcdma and dma-channels from the binding description. Signed-off-by: Radhey Shyam Pandey --- Changes since RFC: New patch. --- Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index 93b6d96..99d06f9 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -42,7 +42,6 @@ Optional properties for AXI DMA: register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the maximum value that is supported by all IP versions. -- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. Optional properties for VDMA: - xlnx,flush-fsync: Tells which channel to Flush on Frame sync. It takes following values: @@ -69,8 +68,6 @@ Optional child node properties for VDMA: enabled/disabled in hardware. - xlnx,enable-vert-flip: Tells vertical flip is enabled/disabled in hardware(S2MM path). -Optional child node properties for AXI DMA: --dma-channels: Number of dma channels in child node. Example: ++++++++ -- 2.7.4