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Tue, 22 Oct 2019 10:00:34 -0700 Received: from xsj-pvapsmtp01 (mailhub.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id x9MH0Wo4030513; Tue, 22 Oct 2019 10:00:32 -0700 Received: from [10.140.184.180] (helo=ubuntu) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iMxWJ-00059f-JZ; Tue, 22 Oct 2019 10:00:31 -0700 Received: by ubuntu (Postfix, from userid 13245) id CDE1410112E; Tue, 22 Oct 2019 22:30:30 +0530 (IST) From: Radhey Shyam Pandey To: vkoul@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, dan.j.williams@intel.com, michal.simek@xilinx.com, anirudha.sarangi@xilinx.com, nick.graumann@gmail.com, andrea.merello@gmail.com, appana.durga.rao@xilinx.com, mcgrof@kernel.org Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Radhey Shyam Pandey Subject: [PATCH -next 3/6] dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP Date: Tue, 22 Oct 2019 22:30:19 +0530 Message-Id: <1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> References: <1571763622-29281-1-git-send-email-radhey.shyam.pandey@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-Result: No--2.053-7.0-31-1 X-imss-scan-details: No--2.053-7.0-31-1;No--2.053-5.0-31-1 X-TM-AS-User-Approved-Sender: No;No X-TM-AS-Result-Xfilter: Match text exemption rules:No X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(376002)(39860400002)(136003)(346002)(396003)(189003)(199004)(478600001)(81156014)(186003)(81166006)(8676002)(26005)(2616005)(6266002)(126002)(446003)(107886003)(11346002)(476003)(4326008)(316002)(50466002)(2906002)(16586007)(42186006)(50226002)(106002)(8936002)(36756003)(70586007)(70206006)(6666004)(356004)(76176011)(48376002)(103686004)(14444005)(47776003)(426003)(486006)(305945005)(7416002)(336012)(5660300002)(51416003)(921003)(1121003);DIR:OUT;SFP:1101;SCL:1;SRVR:SN4PR0201MB3614;H:xsj-pvapsmtpgw01;FPR:;SPF:Pass;LANG:en;PTR:unknown-60-83.xilinx.com;MX:1;A:1; MIME-Version: 1.0 Content-Type: text/plain X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 6ea22e8d-3a24-4563-53d8-08d757115e6c X-MS-TrafficTypeDiagnostic: SN4PR0201MB3614: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:1775; X-Forefront-PRVS: 01986AE76B X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: v7eAm6BwoA0HZ1h1AAPgAVSIXvErRJHo0OGJjQK59Nyo9EmPX0p1FZTZ7+ZvcvSFhlRBFArLoB+O8XNvovDVmI3yVbDr0r96q6c/LR3cv+26wngxBlinHd5XWRxTUxLqHeXtZg3rq4oz2HoMOSV24si9vulLB4v3VJ4Q7pnr0FPgRF8Mq0jPJBr6nyLfJn4z6eFy0On00akZ6cAWtR06jM8k9Tn3P/7dMV9niDMFrnj2tQJrmdznGpO4t4nhm2gyu78Yx3hgkolD0fAfvotzrFrWWfZEPIXni9trCDTvsVvHYWHOqUDSdpNd8zynEMANEkYlQY+fQveDBFlXc/T1HmHqXazhXjk657UhvXJ6WlriJOYWO3AGSzWU4oi2JPNZ18mxaB94v4ZOfcCjdZlTeNgRovdcvS4lSsS3C1HouRFKfl7jjkTuj0prbYz0JhvV X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2019 17:00:40.4911 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ea22e8d-3a24-4563-53d8-08d757115e6c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c;Ip=[149.199.60.83];Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB3614 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access (AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides a scatter-gather interface with multiple channel support with independent configuration. Signed-off-by: Radhey Shyam Pandey --- Keep compatible string one per line. Suggested by Rob. Reuse the existing xlnx,axi-dma-* channel names. Suggested by Rob. --- .../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt index d4ba1cb..325aca5 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt +++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt @@ -11,11 +11,16 @@ is to receive from the device. Xilinx AXI CDMA engine, it does transfers between memory-mapped source address and a memory-mapped destination address. +Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream +target devices. It can be configured to have up to 16 independent transmit +and receive channels. + Required properties: - compatible: Should be one of- "xlnx,axi-vdma-1.00.a" "xlnx,axi-dma-1.00.a" "xlnx,axi-cdma-1.00.a" + "xlnx,axi-mcdma-1.00.a" - #dma-cells: Should be <1>, see "dmas" property below - reg: Should contain VDMA registers location and length. - xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). @@ -31,7 +36,7 @@ Required properties: "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" For CDMA: Required elements: "s_axi_lite_aclk", "m_axi_aclk" - For AXIDMA: + For AXIDMA and MCDMA: Required elements: "s_axi_lite_aclk" Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", "m_axi_sg_aclk" @@ -39,7 +44,7 @@ Required properties: Required properties for VDMA: - xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. -Optional properties for AXI DMA: +Optional properties for AXI DMA and MCDMA: - xlnx,sg-length-width: Should be set to the width in bits of the length register as configured in h/w. Takes values {8...26}. If the property is missing or invalid then the default value 23 is used. This is the @@ -56,8 +61,8 @@ Required child node properties: For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or "xlnx,axi-vdma-s2mm-channel". For CDMA: It should be "xlnx,axi-cdma-channel". - For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or - "xlnx,axi-dma-s2mm-channel". + For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" + or "xlnx,axi-dma-s2mm-channel". - interrupts: Should contain per channel VDMA interrupts. - xlnx,datawidth: Should contain the stream data width, take values {32,64...1024}. @@ -70,6 +75,8 @@ Optional child node properties for VDMA: enabled/disabled in hardware. - xlnx,enable-vert-flip: Tells vertical flip is enabled/disabled in hardware(S2MM path). +Optional child node properties for MCDMA: +- dma-channels: Number of dma channels in child node. Example: ++++++++ -- 2.7.4