From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.6 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0CC67C433E2 for ; Thu, 14 May 2020 16:11:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id D8F59206DC for ; Thu, 14 May 2020 16:11:47 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mQGQsvBo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727933AbgENQLr (ORCPT ); Thu, 14 May 2020 12:11:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726073AbgENQLr (ORCPT ); Thu, 14 May 2020 12:11:47 -0400 Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21EA7C061A0C for ; Thu, 14 May 2020 09:11:46 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id d184so1512631pfd.4 for ; Thu, 14 May 2020 09:11:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=APuaLgIC8QwM4HVjAlkT/Q/E4FOhXs/Y+oj3WvF1K8Q=; b=mQGQsvBohAwHSmGMdJkoWBlfGJiVrUzdEnS9Jk2tgFVbIkdKIy+JDBVgw+T2lNnvII IgRSmEQSUBMOCxXCS68zA+oJ4uLTPQQ0/CaUYwE8HysRc3ve6u8Nk44TKzkDAyr1+GvV EHQrvk0VemZzCmfaa5NazBkf4K3LKMCZfDkVvUD4bUNZEMZKPFgZCIYQIZN/Cq4bojta JfRVbsZaTJMpoJFqNZiPnkXUkA/vWYSZDKPTDv3RtNAghICy5Vhww1ENPs6OWbZ/vEpb za5XiT9Mwim7TtWgysVWYnvNgBA3wzHIW0ma0JjpXj4Aq4RqE4NaTAtdGtlTeoEsWUN7 aQBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=APuaLgIC8QwM4HVjAlkT/Q/E4FOhXs/Y+oj3WvF1K8Q=; b=Nue1tXfszHPk1h3r2fYysbwvKJqECS+ms/Oj6jbXj4ubNdaDoNOfQDKUhdL0MmrxxB uswpfsnSziPg573Ccn0bcKIMjX5jTTik41p1T2SSWFc6wgKUytBIamL7+sPxGshmYeY/ /zVkS7FLrfARqWFFYLGZEMDpM8ZTznOy305dXS7X2iEV8uSZhidfE8Cwh0zX/xeMcOWE NjR1YP8GMwDWoUKE6glI6iBAqQJf2GfDussiLZGx/sOE6AEH8UVIsK/WB85zGxRV0Kkp HgGrUQ/6xW1j4hejJ4M1osZXOvbgX0ub4zKPiochZsHk0SQSid0u1gI1ZPb+k86+r+8O c1Aw== X-Gm-Message-State: AOAM532Kg/HF081ak3/9Gp5NeMU+f9WhMp1bEkjuMc50iQOhRtifd6Bk +4BJ0whvzAxS9hFWX9xf0q8= X-Google-Smtp-Source: ABdhPJwS6b90IBbLq7Bu8zFNMTmjukuliSI6GNd3G/1q7ScpIxaYaWmA/P2MaqU5yssWGQiS8XUVgg== X-Received: by 2002:aa7:8c47:: with SMTP id e7mr4890183pfd.98.1589472705523; Thu, 14 May 2020 09:11:45 -0700 (PDT) Received: from localhost.localdomain ([106.215.24.137]) by smtp.gmail.com with ESMTPSA id t5sm2331755pgp.80.2020.05.14.09.11.41 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 14 May 2020 09:11:44 -0700 (PDT) From: Amit Singh Tomar To: andre.przywara@arm.com, vkoul@kernel.org, afaerber@suse.de, manivannan.sadhasivam@linaro.org Cc: dan.j.williams@intel.com, cristian.ciocaltea@gmail.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-actions@lists.infradead.org Subject: [PATCH v1 1/9] dmaengine: Actions: get rid of bit fields from dma descriptor Date: Thu, 14 May 2020 21:40:49 +0530 Message-Id: <1589472657-3930-2-git-send-email-amittomer25@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1589472657-3930-1-git-send-email-amittomer25@gmail.com> References: <1589472657-3930-1-git-send-email-amittomer25@gmail.com> Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org At the moment, Driver uses bit fields to describe registers of the DMA descriptor structure that makes it less portable and maintainable, and Andre suugested(and even sketched important bits for it) to make use of array to describe this DMA descriptors instead. It gives the flexibility while extending support for other platform such as Actions S700. This commit removes the "owl_dma_lli_hw" (that includes bit-fields) and uses array to describe DMA descriptor. Suggested-by: Andre Przywara Signed-off-by: Amit Singh Tomar --- Changes since RFC: * No change from RFC. --- drivers/dma/owl-dma.c | 77 ++++++++++++++++++++++----------------------------- 1 file changed, 33 insertions(+), 44 deletions(-) diff --git a/drivers/dma/owl-dma.c b/drivers/dma/owl-dma.c index c683051257fd..b0d80a2fa383 100644 --- a/drivers/dma/owl-dma.c +++ b/drivers/dma/owl-dma.c @@ -120,30 +120,18 @@ #define BIT_FIELD(val, width, shift, newshift) \ ((((val) >> (shift)) & ((BIT(width)) - 1)) << (newshift)) -/** - * struct owl_dma_lli_hw - Hardware link list for dma transfer - * @next_lli: physical address of the next link list - * @saddr: source physical address - * @daddr: destination physical address - * @flen: frame length - * @fcnt: frame count - * @src_stride: source stride - * @dst_stride: destination stride - * @ctrla: dma_mode and linklist ctrl config - * @ctrlb: interrupt config - * @const_num: data for constant fill - */ -struct owl_dma_lli_hw { - u32 next_lli; - u32 saddr; - u32 daddr; - u32 flen:20; - u32 fcnt:12; - u32 src_stride; - u32 dst_stride; - u32 ctrla; - u32 ctrlb; - u32 const_num; +/* Describe DMA descriptor, hardware link list for dma transfer */ +enum owl_dmadesc_offsets { + OWL_DMADESC_NEXT_LLI = 0, + OWL_DMADESC_SADDR, + OWL_DMADESC_DADDR, + OWL_DMADESC_FLEN, + OWL_DMADESC_SRC_STRIDE, + OWL_DMADESC_DST_STRIDE, + OWL_DMADESC_CTRLA, + OWL_DMADESC_CTRLB, + OWL_DMADESC_CONST_NUM, + OWL_DMADESC_SIZE }; /** @@ -153,7 +141,7 @@ struct owl_dma_lli_hw { * @node: node for txd's lli_list */ struct owl_dma_lli { - struct owl_dma_lli_hw hw; + u32 hw[OWL_DMADESC_SIZE]; dma_addr_t phys; struct list_head node; }; @@ -351,8 +339,9 @@ static struct owl_dma_lli *owl_dma_add_lli(struct owl_dma_txd *txd, list_add_tail(&next->node, &txd->lli_list); if (prev) { - prev->hw.next_lli = next->phys; - prev->hw.ctrla |= llc_hw_ctrla(OWL_DMA_MODE_LME, 0); + prev->hw[OWL_DMADESC_NEXT_LLI] = next->phys; + prev->hw[OWL_DMADESC_CTRLA] |= + llc_hw_ctrla(OWL_DMA_MODE_LME, 0); } return next; @@ -365,8 +354,7 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan, struct dma_slave_config *sconfig, bool is_cyclic) { - struct owl_dma_lli_hw *hw = &lli->hw; - u32 mode; + u32 mode, ctrlb; mode = OWL_DMA_MODE_PW(0); @@ -407,22 +395,22 @@ static inline int owl_dma_cfg_lli(struct owl_dma_vchan *vchan, return -EINVAL; } - hw->next_lli = 0; /* One link list by default */ - hw->saddr = src; - hw->daddr = dst; - - hw->fcnt = 1; /* Frame count fixed as 1 */ - hw->flen = len; /* Max frame length is 1MB */ - hw->src_stride = 0; - hw->dst_stride = 0; - hw->ctrla = llc_hw_ctrla(mode, - OWL_DMA_LLC_SAV_LOAD_NEXT | - OWL_DMA_LLC_DAV_LOAD_NEXT); + lli->hw[OWL_DMADESC_CTRLA] = llc_hw_ctrla(mode, + OWL_DMA_LLC_SAV_LOAD_NEXT | + OWL_DMA_LLC_DAV_LOAD_NEXT); if (is_cyclic) - hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_BLOCK); + ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_BLOCK); else - hw->ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK); + ctrlb = llc_hw_ctrlb(OWL_DMA_INTCTL_SUPER_BLOCK); + + lli->hw[OWL_DMADESC_NEXT_LLI] = 0; + lli->hw[OWL_DMADESC_SADDR] = src; + lli->hw[OWL_DMADESC_DADDR] = dst; + lli->hw[OWL_DMADESC_SRC_STRIDE] = 0; + lli->hw[OWL_DMADESC_DST_STRIDE] = 0; + lli->hw[OWL_DMADESC_FLEN] = len | 1 << 20; + lli->hw[OWL_DMADESC_CTRLB] = ctrlb; return 0; } @@ -754,7 +742,8 @@ static u32 owl_dma_getbytes_chan(struct owl_dma_vchan *vchan) /* Start from the next active node */ if (lli->phys == next_lli_phy) { list_for_each_entry(lli, &txd->lli_list, node) - bytes += lli->hw.flen; + bytes += lli->hw[OWL_DMADESC_FLEN] & + GENMASK(19, 0); break; } } @@ -785,7 +774,7 @@ static enum dma_status owl_dma_tx_status(struct dma_chan *chan, if (vd) { txd = to_owl_txd(&vd->tx); list_for_each_entry(lli, &txd->lli_list, node) - bytes += lli->hw.flen; + bytes += lli->hw[OWL_DMADESC_FLEN] & GENMASK(19, 0); } else { bytes = owl_dma_getbytes_chan(vchan); } -- 2.7.4