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From: Dave Jiang <dave.jiang@intel.com>
To: vkoul@kernel.org, tglx@linutronix.de, mingo@redhat.com,
	bp@alien8.de, hpa@zytor.com, bhelgaas@google.com,
	gregkh@linuxfoundation.org, arnd@arndb.de
Cc: dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
	x86@kernel.org, dan.j.williams@intel.com, ashok.raj@intel.com,
	fenghua.yu@intel.com, tony.luck@intel.com, jing.lin@intel.com,
	sanjay.k.kumar@intel.com, dave.hansen@intel.com
Subject: [PATCH v2 3/9] x86/asm: add enqcmds() to support ENQCMDS instruction
Date: Mon, 18 May 2020 11:53:39 -0700	[thread overview]
Message-ID: <158982801913.37989.12577827391856760995.stgit@djiang5-desk3.ch.intel.com> (raw)
In-Reply-To: <158982749959.37989.2096629611303670415.stgit@djiang5-desk3.ch.intel.com>

Currently, the MOVDIR64B instruction is used to atomically
submit 64-byte work descriptors to devices. Although it can
encounter errors like faults, MOVDIR64B can not report back on
errors from the device itself. This means that MOVDIR64B users
need to separately interact with a device to see if a descriptor
was successfully queued, which slows down device interactions.

ENQCMD and ENQCMDS also atomically submit 64-byte work
descriptors to devices. But, they *can* report back errors
directly from the device, such as if the device was busy, or
there was an error made in composing the descriptor. This
immediate feedback from the submission instruction itself
reduces the number of interactions with the device and can
greatly increase efficiency.

ENQCMD can be used at any privilege level, but can effectively
only submit work on behalf of the current process. ENQCMDS is a
ring0-only instruction and can explicitly specify a process
context instead of being tied to the current process or needing
to reprogram the IA32_PASID MSR.

Use ENQCMDS for work submission within the kernel because a
Process Address ID (PASID) is setup to translate the kernel
virtual address space. This PASID is provided to ENQCMDS from
the descriptor structure submitted to the device and not retrieved
from IA32_PASID MSR, which is setup for the current user address space.

See Intel Software Developer’s Manual for more information on the
instructions.

Add enqcmds() in x86 io.h instead of special_insns.h. MOVDIR64B
instruction can be used for other purposes. A wrapper was introduced
in io.h for its command submission usage. ENQCMDS has a single
purpose of submit 64-byte commands to supported devices and should
be called directly.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Tony Luck <tony.luck@intel.com>
---
 arch/x86/include/asm/io.h |   28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 56421666115e..049d78d85226 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -424,4 +424,32 @@ static inline void iosubmit_cmds512(void __iomem *dst, const void *src,
 	}
 }
 
+/**
+ * enqcmds - copy a 512 bits data unit to single MMIO location
+ * @dst: destination, in MMIO space (must be 512-bit aligned)
+ * @src: source
+ *
+ * Submit data from kernel space to MMIO space, in a unit of 512 bits.
+ * Order of data access is not guaranteed, nor is a memory barrier
+ * performed afterwards. The command returns false (0) on failure, and true (1)
+ * on success.
+ *
+ * Warning: Do not use this helper unless your driver has checked that the CPU
+ * instruction is supported on the platform.
+ */
+static inline bool enqcmds(void __iomem *dst, const void *src)
+{
+	bool retry;
+
+	/* ENQCMDS [rdx], rax */
+	asm volatile(".byte 0xf3, 0x0f, 0x38, 0xf8, 0x02, 0x66, 0x90\t\n"
+		     "setz %0\t\n"
+		     : "=r"(retry) : "a" (dst), "d" (src));
+	/* Submission failure is indicated via EFLAGS.ZF=1 */
+	if (retry)
+		return false;
+
+	return true;
+}
+
 #endif /* _ASM_X86_IO_H */


  parent reply	other threads:[~2020-05-18 18:53 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-18 18:53 [PATCH v2 0/9] Add shared workqueue support for idxd driver Dave Jiang
2020-05-18 18:53 ` [PATCH v2 1/9] x86/cpufeatures: Enumerate ENQCMD and ENQCMDS instructions Dave Jiang
2020-05-18 18:53 ` [PATCH v2 2/9] x86/asm: move the raw asm in iosubmit_cmds512() to special_insns.h Dave Jiang
2020-05-18 18:53 ` Dave Jiang [this message]
2020-05-18 18:53 ` [PATCH v2 4/9] dmaengine: idxd: add work queue drain support Dave Jiang
2020-05-18 18:53 ` [PATCH v2 5/9] dmaengine: idxd: move submission to sbitmap_queue Dave Jiang
2020-05-18 18:53 ` [PATCH v2 6/9] dmaengine: idxd: add shared workqueue support Dave Jiang
2020-05-18 18:54 ` [PATCH v2 7/9] dmaengine: idxd: clean up descriptors with fault error Dave Jiang
2020-05-18 18:54 ` [PATCH v2 8/9] dmaengine: idxd: add leading / for sysfspath in ABI documentation Dave Jiang
2020-05-18 18:54 ` [PATCH v2 9/9] dmaengine: idxd: add ABI documentation for shared wq Dave Jiang
2020-06-01 22:09 ` [PATCH v2 0/9] Add shared workqueue support for idxd driver Dave Jiang
2020-06-03  6:33   ` Vinod Koul
2020-06-03 15:30     ` Dave Jiang

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