* [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
2020-06-19 8:04 [PATCH v5] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL
@ 2020-06-19 8:04 ` EastL
2020-06-19 9:36 ` Matthias Brugger
2020-06-19 8:05 ` [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL
2020-06-19 8:05 ` [PATCH v5 4/4] dmaengine: mediatek-cqdma: fix compatible EastL
2 siblings, 1 reply; 9+ messages in thread
From: EastL @ 2020-06-19 8:04 UTC (permalink / raw)
To: Sean Wang
Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine,
linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
wsd_upstream, EastL
Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6779 SoC or other similar Mediatek SoCs.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
.../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++
1 file changed, 114 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
new file mode 100644
index 0000000..e6fdf05
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Command-Queue DMA controller Device Tree Binding
+
+maintainers:
+ - EastL Lee <EastL.Lee@mediatek.com>
+
+description:
+ MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
+ is dedicated to memory-to-memory transfer through queue based
+ descriptor management.
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ "#dma-cells":
+ minimum: 1
+ maximum: 255
+ description:
+ Used to provide DMA controller specific information.
+
+ compatible:
+ oneOf:
+ - const: mediatek,common-cqdma
+ - const: mediatek,mt6765-cqdma
+ - const: mediatek,mt6779-cqdma
+
+ reg:
+ minItems: 1
+ maxItems: 5
+ description:
+ A base address of MediaTek Command-Queue DMA controller,
+ a channel will have a set of base address.
+
+ interrupts:
+ minItems: 1
+ maxItems: 5
+ description:
+ A interrupt number of MediaTek Command-Queue DMA controller,
+ one interrupt number per dma-channels.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: cqdma
+
+ dma-channel-mask:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ For DMA capability, We will know the addressing capability of
+ MediaTek Command-Queue DMA controller through dma-channel-mask.
+ items:
+ minItems: 1
+ maxItems: 63
+
+ dma-channels:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Number of DMA channels supported by MediaTek Command-Queue DMA
+ controller, support up to five.
+ items:
+ minItems: 1
+ maxItems: 5
+
+ dma-requests:
+ $ref: /schemas/types.yaml#definitions/uint32
+ description:
+ Number of DMA request (virtual channel) supported by MediaTek
+ Command-Queue DMA controller, support up to 32.
+ items:
+ minItems: 1
+ maxItems: 32
+
+required:
+ - "#dma-cells"
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - dma-channel-mask
+ - dma-channels
+ - dma-requests
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt6779-clk.h>
+ cqdma: dma-controller@10212000 {
+ compatible = "mediatek,mt6779-cqdma";
+ reg = <0x10212000 0x80>,
+ <0x10212080 0x80>,
+ <0x10212100 0x80>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
+ clock-names = "cqdma";
+ dma-channel-mask = <63>;
+ dma-channels = <3>;
+ dma-requests = <32>;
+ #dma-cells = <1>;
+ };
+
+...
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
2020-06-19 8:04 ` [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL
@ 2020-06-19 9:36 ` Matthias Brugger
2020-07-01 8:38 ` EastL
0 siblings, 1 reply; 9+ messages in thread
From: Matthias Brugger @ 2020-06-19 9:36 UTC (permalink / raw)
To: EastL, Sean Wang
Cc: vkoul, robh+dt, mark.rutland, dmaengine, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream
On 19/06/2020 10:04, EastL wrote:
> Document the devicetree bindings for MediaTek Command-Queue DMA controller
> which could be found on MT6779 SoC or other similar Mediatek SoCs.
>
> Signed-off-by: EastL <EastL.Lee@mediatek.com>
Still missing the full name.
> ---
> .../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++
> 1 file changed, 114 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> new file mode 100644
> index 0000000..e6fdf05
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> @@ -0,0 +1,114 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
You missed the brackets ().
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Command-Queue DMA controller Device Tree Binding
> +
> +maintainers:
> + - EastL Lee <EastL.Lee@mediatek.com>
> +
> +description:
> + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> + is dedicated to memory-to-memory transfer through queue based
> + descriptor management.
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + "#dma-cells":
> + minimum: 1
> + maximum: 255
> + description:
> + Used to provide DMA controller specific information.
> +
> + compatible:
> + oneOf:
> + - const: mediatek,common-cqdma
What is the common-cqdma for if we have only one compatible specifying the SoC.
Actually I'm not a great fan of the common-cqdma thing. I'd prefer a fallback
compatible that has the name of the first SoC implementing the same device.
Regards,
Matthias
> + - const: mediatek,mt6765-cqdma
> + - const: mediatek,mt6779-cqdma
> +
> + reg:
> + minItems: 1
> + maxItems: 5
> + description:
> + A base address of MediaTek Command-Queue DMA controller,
> + a channel will have a set of base address.
> +
> + interrupts:
> + minItems: 1
> + maxItems: 5
> + description:
> + A interrupt number of MediaTek Command-Queue DMA controller,
> + one interrupt number per dma-channels.
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + const: cqdma
> +
> + dma-channel-mask:
> + $ref: /schemas/types.yaml#definitions/uint32
> + description:
> + For DMA capability, We will know the addressing capability of
> + MediaTek Command-Queue DMA controller through dma-channel-mask.
> + items:
> + minItems: 1
> + maxItems: 63
> +
> + dma-channels:
> + $ref: /schemas/types.yaml#definitions/uint32
> + description:
> + Number of DMA channels supported by MediaTek Command-Queue DMA
> + controller, support up to five.
> + items:
> + minItems: 1
> + maxItems: 5
> +
> + dma-requests:
> + $ref: /schemas/types.yaml#definitions/uint32
> + description:
> + Number of DMA request (virtual channel) supported by MediaTek
> + Command-Queue DMA controller, support up to 32.
> + items:
> + minItems: 1
> + maxItems: 32
> +
> +required:
> + - "#dma-cells"
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - dma-channel-mask
> + - dma-channels
> + - dma-requests
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/mt6779-clk.h>
> + cqdma: dma-controller@10212000 {
> + compatible = "mediatek,mt6779-cqdma";
> + reg = <0x10212000 0x80>,
> + <0x10212080 0x80>,
> + <0x10212100 0x80>;
> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> + clock-names = "cqdma";
> + dma-channel-mask = <63>;
> + dma-channels = <3>;
> + dma-requests = <32>;
> + #dma-cells = <1>;
> + };
> +
> +...
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
2020-06-19 9:36 ` Matthias Brugger
@ 2020-07-01 8:38 ` EastL
2020-07-01 15:06 ` Matthias Brugger
0 siblings, 1 reply; 9+ messages in thread
From: EastL @ 2020-07-01 8:38 UTC (permalink / raw)
To: Matthias Brugger
Cc: Sean Wang, vkoul, robh+dt, mark.rutland, dmaengine, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream
On Fri, 2020-06-19 at 11:36 +0200, Matthias Brugger wrote:
>
> On 19/06/2020 10:04, EastL wrote:
> > Document the devicetree bindings for MediaTek Command-Queue DMA controller
> > which could be found on MT6779 SoC or other similar Mediatek SoCs.
> >
> > Signed-off-by: EastL <EastL.Lee@mediatek.com>
>
> Still missing the full name.
Sorry I thought it was only needed in the yaml file
I will fix in next version.
>
> > ---
> > .../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++
> > 1 file changed, 114 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > new file mode 100644
> > index 0000000..e6fdf05
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > @@ -0,0 +1,114 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>
> You missed the brackets ().
OK
>
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Command-Queue DMA controller Device Tree Binding
> > +
> > +maintainers:
> > + - EastL Lee <EastL.Lee@mediatek.com>
> > +
> > +description:
> > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> > + is dedicated to memory-to-memory transfer through queue based
> > + descriptor management.
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + "#dma-cells":
> > + minimum: 1
> > + maximum: 255
> > + description:
> > + Used to provide DMA controller specific information.
> > +
> > + compatible:
> > + oneOf:
> > + - const: mediatek,common-cqdma
>
> What is the common-cqdma for if we have only one compatible specifying the SoC.
> Actually I'm not a great fan of the common-cqdma thing. I'd prefer a fallback
> compatible that has the name of the first SoC implementing the same device.
>
> Regards,
> Matthias
>
OK, I'll remove common compatible.
> > + - const: mediatek,mt6765-cqdma
> > + - const: mediatek,mt6779-cqdma
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A base address of MediaTek Command-Queue DMA controller,
> > + a channel will have a set of base address.
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A interrupt number of MediaTek Command-Queue DMA controller,
> > + one interrupt number per dma-channels.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: cqdma
> > +
> > + dma-channel-mask:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + For DMA capability, We will know the addressing capability of
> > + MediaTek Command-Queue DMA controller through dma-channel-mask.
> > + items:
> > + minItems: 1
> > + maxItems: 63
> > +
> > + dma-channels:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + Number of DMA channels supported by MediaTek Command-Queue DMA
> > + controller, support up to five.
> > + items:
> > + minItems: 1
> > + maxItems: 5
> > +
> > + dma-requests:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + Number of DMA request (virtual channel) supported by MediaTek
> > + Command-Queue DMA controller, support up to 32.
> > + items:
> > + minItems: 1
> > + maxItems: 32
> > +
> > +required:
> > + - "#dma-cells"
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - dma-channel-mask
> > + - dma-channels
> > + - dma-requests
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/mt6779-clk.h>
> > + cqdma: dma-controller@10212000 {
> > + compatible = "mediatek,mt6779-cqdma";
> > + reg = <0x10212000 0x80>,
> > + <0x10212080 0x80>,
> > + <0x10212100 0x80>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> > + clock-names = "cqdma";
> > + dma-channel-mask = <63>;
> > + dma-channels = <3>;
> > + dma-requests = <32>;
> > + #dma-cells = <1>;
> > + };
> > +
> > +...
> >
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
2020-07-01 8:38 ` EastL
@ 2020-07-01 15:06 ` Matthias Brugger
0 siblings, 0 replies; 9+ messages in thread
From: Matthias Brugger @ 2020-07-01 15:06 UTC (permalink / raw)
To: EastL
Cc: Sean Wang, vkoul, robh+dt, mark.rutland, dmaengine, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream
On 01/07/2020 10:38, EastL wrote:
> On Fri, 2020-06-19 at 11:36 +0200, Matthias Brugger wrote:
>>
>> On 19/06/2020 10:04, EastL wrote:
>>> Document the devicetree bindings for MediaTek Command-Queue DMA controller
>>> which could be found on MT6779 SoC or other similar Mediatek SoCs.
>>>
>>> Signed-off-by: EastL <EastL.Lee@mediatek.com>
>>
>> Still missing the full name.
>
> Sorry I thought it was only needed in the yaml file
> I will fix in next version.\
Just to make sure there is no missunderstanding, I mean your git settings. Your
Signed-off-by should look like:
EastL Lee <EastL.Lee@mediatek.com>
Regards,
Matthias
>>
>>> ---
>>> .../devicetree/bindings/dma/mtk-cqdma.yaml | 114 +++++++++++++++++++++
>>> 1 file changed, 114 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>> new file mode 100644
>>> index 0000000..e6fdf05
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
>>> @@ -0,0 +1,114 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>
>> You missed the brackets ().
> OK
>>
>>> +%YAML 1.2
>>> +---
>>> +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> +
>>> +title: MediaTek Command-Queue DMA controller Device Tree Binding
>>> +
>>> +maintainers:
>>> + - EastL Lee <EastL.Lee@mediatek.com>
>>> +
>>> +description:
>>> + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
>>> + is dedicated to memory-to-memory transfer through queue based
>>> + descriptor management.
>>> +
>>> +allOf:
>>> + - $ref: "dma-controller.yaml#"
>>> +
>>> +properties:
>>> + "#dma-cells":
>>> + minimum: 1
>>> + maximum: 255
>>> + description:
>>> + Used to provide DMA controller specific information.
>>> +
>>> + compatible:
>>> + oneOf:
>>> + - const: mediatek,common-cqdma
>>
>> What is the common-cqdma for if we have only one compatible specifying the SoC.
>> Actually I'm not a great fan of the common-cqdma thing. I'd prefer a fallback
>> compatible that has the name of the first SoC implementing the same device.
>>
>> Regards,
>> Matthias
>>
> OK, I'll remove common compatible.
>
>>> + - const: mediatek,mt6765-cqdma
>>> + - const: mediatek,mt6779-cqdma
>>> +
>>> + reg:
>>> + minItems: 1
>>> + maxItems: 5
>>> + description:
>>> + A base address of MediaTek Command-Queue DMA controller,
>>> + a channel will have a set of base address.
>>> +
>>> + interrupts:
>>> + minItems: 1
>>> + maxItems: 5
>>> + description:
>>> + A interrupt number of MediaTek Command-Queue DMA controller,
>>> + one interrupt number per dma-channels.
>>> +
>>> + clocks:
>>> + maxItems: 1
>>> +
>>> + clock-names:
>>> + const: cqdma
>>> +
>>> + dma-channel-mask:
>>> + $ref: /schemas/types.yaml#definitions/uint32
>>> + description:
>>> + For DMA capability, We will know the addressing capability of
>>> + MediaTek Command-Queue DMA controller through dma-channel-mask.
>>> + items:
>>> + minItems: 1
>>> + maxItems: 63
>>> +
>>> + dma-channels:
>>> + $ref: /schemas/types.yaml#definitions/uint32
>>> + description:
>>> + Number of DMA channels supported by MediaTek Command-Queue DMA
>>> + controller, support up to five.
>>> + items:
>>> + minItems: 1
>>> + maxItems: 5
>>> +
>>> + dma-requests:
>>> + $ref: /schemas/types.yaml#definitions/uint32
>>> + description:
>>> + Number of DMA request (virtual channel) supported by MediaTek
>>> + Command-Queue DMA controller, support up to 32.
>>> + items:
>>> + minItems: 1
>>> + maxItems: 32
>>> +
>>> +required:
>>> + - "#dma-cells"
>>> + - compatible
>>> + - reg
>>> + - interrupts
>>> + - clocks
>>> + - clock-names
>>> + - dma-channel-mask
>>> + - dma-channels
>>> + - dma-requests
>>> +
>>> +additionalProperties: false
>>> +
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/interrupt-controller/irq.h>
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> + #include <dt-bindings/clock/mt6779-clk.h>
>>> + cqdma: dma-controller@10212000 {
>>> + compatible = "mediatek,mt6779-cqdma";
>>> + reg = <0x10212000 0x80>,
>>> + <0x10212080 0x80>,
>>> + <0x10212100 0x80>;
>>> + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
>>> + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
>>> + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
>>> + clock-names = "cqdma";
>>> + dma-channel-mask = <63>;
>>> + dma-channels = <3>;
>>> + dma-requests = <32>;
>>> + #dma-cells = <1>;
>>> + };
>>> +
>>> +...
>>>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability
2020-06-19 8:04 [PATCH v5] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL
2020-06-19 8:04 ` [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL
@ 2020-06-19 8:05 ` EastL
2020-06-19 9:39 ` Matthias Brugger
2020-06-19 8:05 ` [PATCH v5 4/4] dmaengine: mediatek-cqdma: fix compatible EastL
2 siblings, 1 reply; 9+ messages in thread
From: EastL @ 2020-06-19 8:05 UTC (permalink / raw)
To: Sean Wang
Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine,
linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
wsd_upstream, EastL
This patch add dma mask for capability.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 905bbcb..ed33c64 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
* @clk: The clock that device internal is using
* @dma_requests: The number of VCs the device supports to
* @dma_channels: The number of PCs the device supports to
+ * @dma_mask: A mask for DMA capability
* @vc: The pointer to all available VCs
* @pc: The pointer to all the underlying PCs
*/
@@ -126,6 +127,7 @@ struct mtk_cqdma_device {
u32 dma_requests;
u32 dma_channels;
+ u32 dma_mask;
struct mtk_cqdma_vchan *vc;
struct mtk_cqdma_pchan **pc;
};
@@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
}
+ if (pdev->dev.of_node)
+ err = of_property_read_u32(pdev->dev.of_node,
+ "dma-channel-mask",
+ &cqdma->dma_mask);
+ if (err) {
+ dev_warn(&pdev->dev,
+ "Using 0 as missing dma-channel-mask property\n");
+ cqdma->dma_mask = 0;
+ }
+
+ if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) {
+ dev_warn(&pdev->dev, "DMA set mask fail\n");
+ return -EINVAL;
+ }
+
cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
sizeof(*cqdma->pc), GFP_KERNEL);
if (!cqdma->pc)
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability
2020-06-19 8:05 ` [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL
@ 2020-06-19 9:39 ` Matthias Brugger
2020-07-01 9:01 ` EastL
0 siblings, 1 reply; 9+ messages in thread
From: Matthias Brugger @ 2020-06-19 9:39 UTC (permalink / raw)
To: EastL, Sean Wang
Cc: vkoul, robh+dt, mark.rutland, dmaengine, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream
On 19/06/2020 10:05, EastL wrote:
> This patch add dma mask for capability.
>
> Signed-off-by: EastL <EastL.Lee@mediatek.com>
> ---
> drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index 905bbcb..ed33c64 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
> * @clk: The clock that device internal is using
> * @dma_requests: The number of VCs the device supports to
> * @dma_channels: The number of PCs the device supports to
> + * @dma_mask: A mask for DMA capability
> * @vc: The pointer to all available VCs
> * @pc: The pointer to all the underlying PCs
> */
> @@ -126,6 +127,7 @@ struct mtk_cqdma_device {
>
> u32 dma_requests;
> u32 dma_channels;
> + u32 dma_mask;
> struct mtk_cqdma_vchan *vc;
> struct mtk_cqdma_pchan **pc;
> };
> @@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
> cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
> }
>
> + if (pdev->dev.of_node)
> + err = of_property_read_u32(pdev->dev.of_node,
> + "dma-channel-mask",
> + &cqdma->dma_mask);
> + if (err) {
> + dev_warn(&pdev->dev,
> + "Using 0 as missing dma-channel-mask property\n");
> + cqdma->dma_mask = 0;
> + }
> +
> + if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) {
> + dev_warn(&pdev->dev, "DMA set mask fail\n");
fail -> failed
With this:
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> + return -EINVAL;
> + }
> +
> cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
> sizeof(*cqdma->pc), GFP_KERNEL);
> if (!cqdma->pc)
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability
2020-06-19 9:39 ` Matthias Brugger
@ 2020-07-01 9:01 ` EastL
0 siblings, 0 replies; 9+ messages in thread
From: EastL @ 2020-07-01 9:01 UTC (permalink / raw)
To: Matthias Brugger
Cc: Sean Wang, vkoul, robh+dt, mark.rutland, dmaengine, linux-kernel,
linux-arm-kernel, linux-mediatek, devicetree, wsd_upstream
On Fri, 2020-06-19 at 11:39 +0200, Matthias Brugger wrote:
>
> On 19/06/2020 10:05, EastL wrote:
> > This patch add dma mask for capability.
> >
> > Signed-off-by: EastL <EastL.Lee@mediatek.com>
> > ---
> > drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++
> > 1 file changed, 17 insertions(+)
> >
> > diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> > index 905bbcb..ed33c64 100644
> > --- a/drivers/dma/mediatek/mtk-cqdma.c
> > +++ b/drivers/dma/mediatek/mtk-cqdma.c
> > @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
> > * @clk: The clock that device internal is using
> > * @dma_requests: The number of VCs the device supports to
> > * @dma_channels: The number of PCs the device supports to
> > + * @dma_mask: A mask for DMA capability
> > * @vc: The pointer to all available VCs
> > * @pc: The pointer to all the underlying PCs
> > */
> > @@ -126,6 +127,7 @@ struct mtk_cqdma_device {
> >
> > u32 dma_requests;
> > u32 dma_channels;
> > + u32 dma_mask;
> > struct mtk_cqdma_vchan *vc;
> > struct mtk_cqdma_pchan **pc;
> > };
> > @@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
> > cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
> > }
> >
> > + if (pdev->dev.of_node)
> > + err = of_property_read_u32(pdev->dev.of_node,
> > + "dma-channel-mask",
> > + &cqdma->dma_mask);
> > + if (err) {
> > + dev_warn(&pdev->dev,
> > + "Using 0 as missing dma-channel-mask property\n");
> > + cqdma->dma_mask = 0;
> > + }
> > +
> > + if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) {
> > + dev_warn(&pdev->dev, "DMA set mask fail\n");
>
> fail -> failed
>
> With this:
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
OK.
>
> > + return -EINVAL;
> > + }
> > +
> > cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
> > sizeof(*cqdma->pc), GFP_KERNEL);
> > if (!cqdma->pc)
> >
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 4/4] dmaengine: mediatek-cqdma: fix compatible
2020-06-19 8:04 [PATCH v5] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL
2020-06-19 8:04 ` [PATCH v5 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL
2020-06-19 8:05 ` [PATCH v5 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL
@ 2020-06-19 8:05 ` EastL
2 siblings, 0 replies; 9+ messages in thread
From: EastL @ 2020-06-19 8:05 UTC (permalink / raw)
To: Sean Wang
Cc: vkoul, robh+dt, mark.rutland, matthias.bgg, dmaengine,
linux-kernel, linux-arm-kernel, linux-mediatek, devicetree,
wsd_upstream, EastL
This patch adds common compatible & platform compatiable.
Signed-off-by: EastL <EastL.Lee@mediatek.com>
---
drivers/dma/mediatek/mtk-cqdma.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index ed33c64..d701ebf 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -546,7 +546,9 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
}
static const struct of_device_id mtk_cqdma_match[] = {
+ { .compatible = "mediatek,common-cqdma" },
{ .compatible = "mediatek,mt6765-cqdma" },
+ { .compatible = "mediatek,mt6779-cqdma" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
--
1.9.1
^ permalink raw reply related [flat|nested] 9+ messages in thread