* [PATCH v2 1/9] dmaengine: fsl-edma: move edma_request functions into drvdata
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 2/9] dmaengine: fsl-edma-common: add condition check for fsl_edma_chan_mux Robin Gong
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
Move fsl_edma_enable_request/fsl_edma_disable_request into drvdata so
that later edma3 could easily be added.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 13 +++++++------
drivers/dma/fsl-edma-common.h | 3 +++
drivers/dma/fsl-edma.c | 10 ++++++++--
drivers/dma/mcf-edma.c | 2 ++
4 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 4550818..ef5294f0 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -42,7 +42,7 @@
#define EDMA_TCD 0x1000
-static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
+void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
{
struct edma_regs *regs = &fsl_chan->edma->regs;
u32 ch = fsl_chan->vchan.chan.chan_id;
@@ -58,6 +58,7 @@ static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
iowrite8(ch, regs->serq);
}
}
+EXPORT_SYMBOL_GPL(fsl_edma_enable_request);
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
{
@@ -164,7 +165,7 @@ int fsl_edma_terminate_all(struct dma_chan *chan)
LIST_HEAD(head);
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
- fsl_edma_disable_request(fsl_chan);
+ fsl_chan->edma->drvdata->dis_req(fsl_chan);
fsl_chan->edesc = NULL;
fsl_chan->idle = true;
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
@@ -181,7 +182,7 @@ int fsl_edma_pause(struct dma_chan *chan)
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
if (fsl_chan->edesc) {
- fsl_edma_disable_request(fsl_chan);
+ fsl_chan->edma->drvdata->dis_req(fsl_chan);
fsl_chan->status = DMA_PAUSED;
fsl_chan->idle = true;
}
@@ -197,7 +198,7 @@ int fsl_edma_resume(struct dma_chan *chan)
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
if (fsl_chan->edesc) {
- fsl_edma_enable_request(fsl_chan);
+ fsl_chan->edma->drvdata->en_req(fsl_chan);
fsl_chan->status = DMA_IN_PROGRESS;
fsl_chan->idle = false;
}
@@ -596,7 +597,7 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
return;
fsl_chan->edesc = to_fsl_edma_desc(vdesc);
fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
- fsl_edma_enable_request(fsl_chan);
+ fsl_chan->edma->drvdata->en_req(fsl_chan);
fsl_chan->status = DMA_IN_PROGRESS;
fsl_chan->idle = false;
}
@@ -640,7 +641,7 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
LIST_HEAD(head);
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
- fsl_edma_disable_request(fsl_chan);
+ fsl_chan->edma->drvdata->dis_req(fsl_chan);
fsl_edma_chan_mux(fsl_chan, 0, false);
fsl_chan->edesc = NULL;
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index ec11697..87c8d7a 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -150,6 +150,8 @@ struct fsl_edma_drvdata {
bool mux_swap;
int (*setup_irq)(struct platform_device *pdev,
struct fsl_edma_engine *fsl_edma);
+ void (*en_req)(struct fsl_edma_chan *fsl_chan);
+ void (*dis_req)(struct fsl_edma_chan *fsl_chan);
};
struct fsl_edma_engine {
@@ -222,6 +224,7 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
}
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
+void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
unsigned int slot, bool enable);
void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
diff --git a/drivers/dma/fsl-edma.c b/drivers/dma/fsl-edma.c
index 90bb72a..95745636 100644
--- a/drivers/dma/fsl-edma.c
+++ b/drivers/dma/fsl-edma.c
@@ -83,7 +83,7 @@ static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
for (ch = 0; ch < fsl_edma->n_chans; ch++) {
if (err & (0x1 << ch)) {
- fsl_edma_disable_request(&fsl_edma->chans[ch]);
+ fsl_edma->drvdata->dis_req(&fsl_edma->chans[ch]);
edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
fsl_edma->chans[ch].status = DMA_ERROR;
fsl_edma->chans[ch].idle = true;
@@ -238,6 +238,8 @@ static struct fsl_edma_drvdata vf610_data = {
.version = v1,
.dmamuxs = DMAMUX_NR,
.setup_irq = fsl_edma_irq_init,
+ .en_req = fsl_edma_enable_request,
+ .dis_req = fsl_edma_disable_request,
};
static struct fsl_edma_drvdata ls1028a_data = {
@@ -245,6 +247,8 @@ static struct fsl_edma_drvdata ls1028a_data = {
.dmamuxs = DMAMUX_NR,
.mux_swap = true,
.setup_irq = fsl_edma_irq_init,
+ .en_req = fsl_edma_enable_request,
+ .dis_req = fsl_edma_disable_request,
};
static struct fsl_edma_drvdata imx7ulp_data = {
@@ -252,6 +256,8 @@ static struct fsl_edma_drvdata imx7ulp_data = {
.dmamuxs = 1,
.has_dmaclk = true,
.setup_irq = fsl_edma2_irq_init,
+ .en_req = fsl_edma_enable_request,
+ .dis_req = fsl_edma_disable_request,
};
static const struct of_device_id fsl_edma_dt_ids[] = {
@@ -444,7 +450,7 @@ static int fsl_edma_suspend_late(struct device *dev)
/* Make sure chan is idle or will force disable. */
if (unlikely(!fsl_chan->idle)) {
dev_warn(dev, "WARN: There is non-idle channel.");
- fsl_edma_disable_request(fsl_chan);
+ fsl_edma->drvdata->dis_req(fsl_chan);
fsl_edma_chan_mux(fsl_chan, 0, false);
}
diff --git a/drivers/dma/mcf-edma.c b/drivers/dma/mcf-edma.c
index e12b754..50e6b9b 100644
--- a/drivers/dma/mcf-edma.c
+++ b/drivers/dma/mcf-edma.c
@@ -174,6 +174,8 @@ static void mcf_edma_irq_free(struct platform_device *pdev,
static struct fsl_edma_drvdata mcf_data = {
.version = v2,
.setup_irq = mcf_edma_irq_init,
+ .en_req = fsl_edma_enable_request,
+ .dis_req = fsl_edma_disable_request,
};
static int mcf_edma_probe(struct platform_device *pdev)
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 2/9] dmaengine: fsl-edma-common: add condition check for fsl_edma_chan_mux
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
2020-07-14 17:41 ` [PATCH v2 1/9] dmaengine: fsl-edma: move edma_request functions into drvdata Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 3/9] dmaengine: fsl-edma-common: add fsl_chan into fsl_edma_fill_tcd Robin Gong
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
Since next edma3 don't have dmamux, add condition check in the common
fsl_edma_free_chan_resources().
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index ef5294f0..d19e8a8 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -642,7 +642,10 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
fsl_chan->edma->drvdata->dis_req(fsl_chan);
- fsl_edma_chan_mux(fsl_chan, 0, false);
+
+ if (fsl_chan->edma->drvdata->dmamuxs)
+ fsl_edma_chan_mux(fsl_chan, 0, false);
+
fsl_chan->edesc = NULL;
vchan_get_all_descriptors(&fsl_chan->vchan, &head);
fsl_edma_unprep_slave_dma(fsl_chan);
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/9] dmaengine: fsl-edma-common: add fsl_chan into fsl_edma_fill_tcd
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
2020-07-14 17:41 ` [PATCH v2 1/9] dmaengine: fsl-edma: move edma_request functions into drvdata Robin Gong
2020-07-14 17:41 ` [PATCH v2 2/9] dmaengine: fsl-edma-common: add condition check for fsl_edma_chan_mux Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 4/9] dmaengine: fsl-edma-common: export fsl_edma_set_tcd_regs Robin Gong
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
For preparing for next edma3 merged so that any member of 'struct fsl_chan'
could be used in fsl_edma_fill_tcd.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index d19e8a8..6ef083c 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -376,7 +376,8 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
}
static inline
-void fsl_edma_fill_tcd(struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
+void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
+ struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst,
u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer,
u16 biter, u16 doff, u32 dlast_sga, bool major_int,
bool disable_req, bool enable_sg)
@@ -504,9 +505,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
doff = fsl_chan->cfg.src_addr_width;
}
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
- fsl_chan->attr, soff, nbytes, 0, iter,
- iter, doff, last_sg, true, false, true);
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
+ dst_addr, fsl_chan->attr, soff, nbytes, 0,
+ iter, iter, doff, last_sg, true, false, true);
dma_buf_next += period_len;
}
@@ -569,16 +570,16 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
iter = sg_dma_len(sg) / nbytes;
if (i < sg_len - 1) {
last_sg = fsl_desc->tcd[(i + 1)].ptcd;
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->attr, soff,
- nbytes, 0, iter, iter, doff, last_sg,
- false, false, true);
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd,
+ src_addr, dst_addr, fsl_chan->attr,
+ soff, nbytes, 0, iter, iter, doff,
+ last_sg, false, false, true);
} else {
last_sg = 0;
- fsl_edma_fill_tcd(fsl_desc->tcd[i].vtcd, src_addr,
- dst_addr, fsl_chan->attr, soff,
- nbytes, 0, iter, iter, doff, last_sg,
- true, true, false);
+ fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd,
+ src_addr, dst_addr, fsl_chan->attr,
+ soff, nbytes, 0, iter, iter, doff,
+ last_sg, true, true, false);
}
}
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 4/9] dmaengine: fsl-edma-common: export fsl_edma_set_tcd_regs
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (2 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 3/9] dmaengine: fsl-edma-common: add fsl_chan into fsl_edma_fill_tcd Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 5/9] dmaengine: fsl-edma3: add fsl-edma3 driver Robin Gong
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
Preparing for edma3 since it need to be called in fsl-edma3.c
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/fsl-edma-common.c | 3 ++-
drivers/dma/fsl-edma-common.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 6ef083c..05d56d8 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -343,7 +343,7 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
}
EXPORT_SYMBOL_GPL(fsl_edma_tx_status);
-static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
+void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
@@ -374,6 +374,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr);
}
+EXPORT_SYMBOL_GPL(fsl_edma_set_tcd_regs);
static inline
void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 87c8d7a..56f29f3 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -249,5 +249,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
void fsl_edma_free_chan_resources(struct dma_chan *chan);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
+void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
+ struct fsl_edma_hw_tcd *tcd);
#endif /* _FSL_EDMA_COMMON_H_ */
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/9] dmaengine: fsl-edma3: add fsl-edma3 driver
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (3 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 4/9] dmaengine: fsl-edma-common: export fsl_edma_set_tcd_regs Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml Robin Gong
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
add fsl-edma3 driver since there are big differences with legacy fsl-edma
including below major items:
1. split memory address for per channel, while all channels share the same
memory address and the same control registers CR/INT..etc.
2. all TCD registers of channels are continuous on legacy edma but split on
edma3.
3. per interrupt per channel on edma3.
4. totally different register layer and add some register such as SBR
5. power domain support, per domain per channel.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/dma/Kconfig | 12 +
drivers/dma/Makefile | 1 +
drivers/dma/fsl-edma-common.c | 105 ++++++++-
drivers/dma/fsl-edma-common.h | 25 +++
drivers/dma/fsl-edma3.c | 493 ++++++++++++++++++++++++++++++++++++++++++
5 files changed, 631 insertions(+), 5 deletions(-)
create mode 100644 drivers/dma/fsl-edma3.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index b70e907..bd39e6b 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -214,6 +214,18 @@ config FSL_EDMA
multiplexing capability for DMA request sources(slot).
This module can be found on Freescale Vybrid and LS-1 SoCs.
+config FSL_EDMA3
+ tristate "Freescale eDMA3 engine support"
+ depends on OF
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ help
+ Support the Freescale/NXP eDMA v3 engine with programmable channel.
+ This driver is based on FSL_EDMA but big changes come such as
+ different interrupt for different channel, different register
+ scope for different channel.
+ This module can be found on Freescale i.MX8QM/QXP/ULP
+
config FSL_QDMA
tristate "NXP Layerscape qDMA engine support"
depends on ARM || ARM64
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index e60f813..f3a21a0 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_DW_EDMA) += dw-edma/
obj-$(CONFIG_EP93XX_DMA) += ep93xx_dma.o
obj-$(CONFIG_FSL_DMA) += fsldma.o
obj-$(CONFIG_FSL_EDMA) += fsl-edma.o fsl-edma-common.o
+obj-$(CONFIG_FSL_EDMA3) += fsl-edma3.o fsl-edma-common.o
obj-$(CONFIG_MCF_EDMA) += mcf-edma.o fsl-edma-common.o
obj-$(CONFIG_FSL_QDMA) += fsl-qdma.o
obj-$(CONFIG_FSL_RAID) += fsl_raid.o
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 05d56d8..e07880c 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -40,6 +40,13 @@
#define EDMA64_ERRH 0x28
#define EDMA64_ERRL 0x2c
+#define EDMA3_CSR 0x00
+#define EDMA3_ES 0x04
+#define EDMA3_INT 0x08
+#define EDMA3_SBR 0x0C
+#define EDMA3_PRI 0x10
+#define EDMA3_TCD 0x20
+
#define EDMA_TCD 0x1000
void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
@@ -78,6 +85,38 @@ void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
}
EXPORT_SYMBOL_GPL(fsl_edma_disable_request);
+void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
+{
+ struct edma_regs *regs = &fsl_chan->regs;
+ u32 val;
+
+ val = edma_readl(fsl_chan->edma, regs->sbr);
+ if (fsl_chan->is_rx)
+ val |= EDMA3_SBR_RD;
+ else
+ val |= EDMA3_SBR_WR;
+
+ if (fsl_chan->is_remote)
+ val &= ~(EDMA3_SBR_RD | EDMA3_SBR_RD);
+
+ edma_writel(fsl_chan->edma, val, regs->sbr);
+
+ val = edma_readl(fsl_chan->edma, regs->cr);
+ val |= EDMA3_CSR_ERQ;
+ edma_writel(fsl_chan->edma, val, regs->cr);
+}
+EXPORT_SYMBOL_GPL(fsl_edma3_enable_request);
+
+void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan)
+{
+ struct edma_regs *regs = &fsl_chan->regs;
+ u32 val = edma_readl(fsl_chan->edma, regs->cr);
+
+ val &= ~EDMA3_CSR_ERQ;
+ edma_writel(fsl_chan->edma, val, regs->cr);
+}
+EXPORT_SYMBOL_GPL(fsl_edma3_disable_request);
+
static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
u32 off, u32 slot, bool enable)
{
@@ -272,13 +311,21 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
struct virt_dma_desc *vdesc, bool in_progress)
{
struct fsl_edma_desc *edesc = fsl_chan->edesc;
- struct edma_regs *regs = &fsl_chan->edma->regs;
- u32 ch = fsl_chan->vchan.chan.chan_id;
+ struct edma_regs *regs;
+ u32 ch;
enum dma_transfer_direction dir = edesc->dirn;
dma_addr_t cur_addr, dma_addr;
size_t len, size;
int i;
+ if (fsl_chan->edma->drvdata->is_split) {
+ regs = &fsl_chan->regs;
+ ch = 0;
+ } else {
+ regs = &fsl_chan->edma->regs;
+ ch = fsl_chan->vchan.chan.chan_id;
+ }
+
/* calculate the total size in this desc */
for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++)
len += le32_to_cpu(edesc->tcd[i].vtcd->nbytes)
@@ -304,6 +351,7 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
len -= size;
if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
len += dma_addr + size - cur_addr;
+ fsl_chan->processed = i;
break;
}
}
@@ -311,6 +359,15 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
return len;
}
+/*
+ * For saving real count for edma3 eeop since thereal count may not be the
+ * transfer size when the edma channel done interrupt triggered.
+ */
+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan)
+{
+ fsl_chan->chn_real_count = fsl_edma_desc_residue(fsl_chan, NULL, true);
+}
+
enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *txstate)
{
@@ -320,8 +377,12 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
unsigned long flags;
status = dma_cookie_status(chan, cookie, txstate);
- if (status == DMA_COMPLETE)
+ if (status == DMA_COMPLETE) {
+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+ txstate->residue = fsl_chan->chn_real_count;
+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
return status;
+ }
if (!txstate)
return fsl_chan->status;
@@ -347,8 +408,16 @@ void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd)
{
struct fsl_edma_engine *edma = fsl_chan->edma;
- struct edma_regs *regs = &fsl_chan->edma->regs;
- u32 ch = fsl_chan->vchan.chan.chan_id;
+ struct edma_regs *regs;
+ u32 ch;
+
+ if (edma->drvdata->is_split) {
+ regs = &fsl_chan->regs;
+ ch = 0;
+ } else {
+ regs = &fsl_chan->edma->regs;
+ ch = fsl_chan->vchan.chan.chan_id;
+ }
/*
* TCD parameters are stored in struct fsl_edma_hw_tcd in little
@@ -372,6 +441,10 @@ void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
edma_writel(edma, le32_to_cpu(tcd->dlast_sga),
®s->tcd[ch].dlast_sga);
+ /* Clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] for edma3 */
+ if (edma->drvdata->is_split)
+ edma_writel(edma, edma_readl(edma, regs->cr), regs->cr);
+
edma_writew(edma, le16_to_cpu(tcd->csr), ®s->tcd[ch].csr);
}
EXPORT_SYMBOL_GPL(fsl_edma_set_tcd_regs);
@@ -416,6 +489,10 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
if (enable_sg)
csr |= EDMA_TCD_CSR_E_SG;
+ /* EEOP for bit6 on edma3 */
+ if (fsl_chan->is_rx && fsl_chan->edma->drvdata->is_split)
+ csr |= EDMA_TCD_CSR_ACTIVE;
+
tcd->csr = cpu_to_le16(csr);
}
@@ -602,6 +679,7 @@ void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
fsl_chan->edma->drvdata->en_req(fsl_chan);
fsl_chan->status = DMA_IN_PROGRESS;
fsl_chan->idle = false;
+ fsl_chan->chn_real_count = 0;
}
EXPORT_SYMBOL_GPL(fsl_edma_xfer_desc);
@@ -632,6 +710,10 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
sizeof(struct fsl_edma_hw_tcd),
32, 0);
+
+ if (fsl_chan->edma->drvdata->is_split)
+ fsl_chan->edma->drvdata->request_irq(fsl_chan);
+
return 0;
}
EXPORT_SYMBOL_GPL(fsl_edma_alloc_chan_resources);
@@ -655,6 +737,10 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
dma_pool_destroy(fsl_chan->tcd_pool);
+
+ if (fsl_chan->edma->drvdata->is_split)
+ fsl_chan->edma->drvdata->free_irq(fsl_chan);
+
fsl_chan->tcd_pool = NULL;
}
EXPORT_SYMBOL_GPL(fsl_edma_free_chan_resources);
@@ -719,4 +805,13 @@ void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
}
EXPORT_SYMBOL_GPL(fsl_edma_setup_regs);
+void fsl_edma3_setup_regs(struct fsl_edma_chan *fsl_chan)
+{
+ fsl_chan->regs.cr = fsl_chan->chan_base + EDMA3_CSR;
+ fsl_chan->regs.intl = fsl_chan->chan_base + EDMA3_INT;
+ fsl_chan->regs.sbr = fsl_chan->chan_base + EDMA3_SBR;
+ fsl_chan->regs.tcd = fsl_chan->chan_base + EDMA3_TCD;
+}
+EXPORT_SYMBOL_GPL(fsl_edma3_setup_regs);
+
MODULE_LICENSE("GPL v2");
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 56f29f3..624f1db 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -25,6 +25,10 @@
#define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0))
#define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0))
+#define EDMA3_SBR_RD BIT(22)
+#define EDMA3_SBR_WR BIT(21)
+#define EDMA3_CSR_ERQ BIT(0)
+
#define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0)))
#define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3)
#define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8)
@@ -103,6 +107,7 @@ struct edma_regs {
void __iomem *intl;
void __iomem *errh;
void __iomem *errl;
+ void __iomem *sbr;
struct fsl_edma_hw_tcd __iomem *tcd;
};
@@ -126,6 +131,18 @@ struct fsl_edma_chan {
u32 dma_dev_size;
enum dma_data_direction dma_dir;
char chan_name[16];
+ /* real transfered count saved for eeop */
+ u32 chn_real_count;
+ /* No. of processed tcd in cyclic */
+ u32 processed;
+ void __iomem *chan_base;
+ int hw_chanid;
+ int priority;
+ int txirq;
+ struct device *dev;
+ bool is_rx;
+ bool is_remote;
+ struct edma_regs regs;
};
struct fsl_edma_desc {
@@ -141,10 +158,12 @@ enum edma_version {
v1, /* 32ch, Vybrid, mpc57x, etc */
v2, /* 64ch Coldfire */
v3, /* 32ch, i.mx7ulp */
+ v4, /* 32ch, i.mx8qm/qxp */
};
struct fsl_edma_drvdata {
enum edma_version version;
+ bool is_split;
u32 dmamuxs;
bool has_dmaclk;
bool mux_swap;
@@ -152,6 +171,8 @@ struct fsl_edma_drvdata {
struct fsl_edma_engine *fsl_edma);
void (*en_req)(struct fsl_edma_chan *fsl_chan);
void (*dis_req)(struct fsl_edma_chan *fsl_chan);
+ int (*request_irq)(struct fsl_edma_chan *fsl_chan);
+ int (*free_irq)(struct fsl_edma_chan *fsl_chan);
};
struct fsl_edma_engine {
@@ -225,6 +246,8 @@ static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd)
void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan);
+void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan);
+void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan);
void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
unsigned int slot, bool enable);
void fsl_edma_free_desc(struct virt_dma_desc *vdesc);
@@ -233,6 +256,7 @@ int fsl_edma_pause(struct dma_chan *chan);
int fsl_edma_resume(struct dma_chan *chan);
int fsl_edma_slave_config(struct dma_chan *chan,
struct dma_slave_config *cfg);
+void fsl_edma_get_realcnt(struct fsl_edma_chan *fsl_chan);
enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
dma_cookie_t cookie, struct dma_tx_state *txstate);
struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
@@ -249,6 +273,7 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan);
void fsl_edma_free_chan_resources(struct dma_chan *chan);
void fsl_edma_cleanup_vchan(struct dma_device *dmadev);
void fsl_edma_setup_regs(struct fsl_edma_engine *edma);
+void fsl_edma3_setup_regs(struct fsl_edma_chan *fsl_chan);
void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan,
struct fsl_edma_hw_tcd *tcd);
diff --git a/drivers/dma/fsl-edma3.c b/drivers/dma/fsl-edma3.c
new file mode 100644
index 00000000..1415682
--- /dev/null
+++ b/drivers/dma/fsl-edma3.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * drivers/dma/fsl-edma3.c
+ *
+ * Copyright 2020 NXP
+ *
+ * Driver for NXP eDMA3 engine which is based on fsl-edma.c. eDMA3 could
+ * be found on i.mx8qm/qxp/8ulp etc.
+ */
+
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_dma.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_domain.h>
+
+#include "fsl-edma-common.h"
+
+#define ARGS_RX BIT(0)
+#define ARGS_REMOTE BIT(1)
+
+/* channel name template define in dts */
+#define CHAN_PREFIX "edma0-chan"
+#define CHAN_POSFIX "-tx"
+
+struct fsl_edma3_engine {
+ unsigned long irqflag;
+ struct fsl_edma_engine fsl_edma;
+};
+
+static struct fsl_edma3_engine *to_fsl_edma3(struct fsl_edma_engine *t)
+{
+ return container_of(t, struct fsl_edma3_engine, fsl_edma);
+}
+
+static irqreturn_t fsl_edma3_irq_handler(int irq, void *dev_id)
+{
+ struct fsl_edma_chan *fsl_chan = dev_id;
+ struct fsl_edma_engine *fsl_edma = fsl_chan->edma;
+ struct edma_regs *regs = &fsl_chan->regs;
+ unsigned int intr;
+ irqreturn_t ret = IRQ_HANDLED;
+
+ spin_lock(&fsl_chan->vchan.lock);
+
+ /* Ignore this interrupt if this channels has been free-ed */
+ if (!fsl_chan->tcd_pool)
+ goto irq_handled;
+
+ intr = edma_readl(fsl_edma, regs->intl);
+ if (!intr) {
+ ret = IRQ_NONE;
+ goto irq_handled;
+ }
+
+ edma_writel(fsl_edma, 1, regs->intl);
+
+ /* Ignore this interrupt since channel has been disabled already */
+ if (!fsl_chan->edesc)
+ goto irq_handled;
+
+ if (!fsl_chan->edesc->iscyclic) {
+ fsl_edma_get_realcnt(fsl_chan);
+ list_del(&fsl_chan->edesc->vdesc.node);
+ vchan_cookie_complete(&fsl_chan->edesc->vdesc);
+ fsl_chan->edesc = NULL;
+ fsl_chan->status = DMA_COMPLETE;
+ fsl_chan->idle = true;
+ } else {
+ vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
+ }
+
+ if (!fsl_chan->edesc)
+ fsl_edma_xfer_desc(fsl_chan);
+
+irq_handled:
+ spin_unlock(&fsl_chan->vchan.lock);
+
+ return ret;
+}
+
+
+static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
+ struct dma_chan *chan, *_chan;
+ struct fsl_edma_chan *fsl_chan;
+
+ if (dma_spec->args_count != 3)
+ return NULL;
+
+ mutex_lock(&fsl_edma->fsl_edma_mutex);
+ list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
+ device_node) {
+ if (chan->client_count)
+ continue;
+ fsl_chan = to_fsl_edma_chan(chan);
+ if (fsl_chan->hw_chanid == dma_spec->args[0]) {
+ chan = dma_get_slave_channel(chan);
+ chan->device->privatecnt++;
+ fsl_chan->priority = dma_spec->args[1];
+ fsl_chan->is_rx = dma_spec->args[2] & ARGS_RX;
+ fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE;
+ mutex_unlock(&fsl_edma->fsl_edma_mutex);
+ return chan;
+ }
+ }
+ mutex_unlock(&fsl_edma->fsl_edma_mutex);
+
+ return NULL;
+}
+
+static int
+fsl_edma3_parse_chanirq(struct platform_device *pdev,
+ struct fsl_edma_chan *fsl_chan, int i)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const char *txirq_name;
+ char chanid[3], id_len = 0;
+ struct resource *res;
+ unsigned long hwid;
+ int ret;
+ /* Get per channel membase */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, i);
+ fsl_chan->chan_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(fsl_chan->chan_base))
+ return PTR_ERR(fsl_chan->chan_base);
+
+ /* Get the hardware chanel id by the channel membase
+ * channel0:0x10000, channel1:0x20000... total 32 channels
+ */
+ fsl_chan->hw_chanid = (res->start >> 16) & 0x1f;
+
+ ret = of_property_read_string_index(np, "interrupt-names", i,
+ &txirq_name);
+ if (ret) {
+ dev_err(&pdev->dev, "read interrupt-names fail.\n");
+ return ret;
+ }
+ /* Get channel id length from dts, one-digit or double-digit */
+ id_len = strlen(txirq_name) - strlen(CHAN_PREFIX) -
+ strlen(CHAN_POSFIX);
+ if (id_len != 2 && id_len != 1) {
+ dev_err(&pdev->dev, "%s is edmaX-chanX-tx in dts?\n",
+ res->name);
+ return -EINVAL;
+ }
+ /* Grab channel id from txirq_name */
+ strlcpy(chanid, txirq_name + strlen(CHAN_PREFIX), id_len + 1);
+
+ /* check if the channel id match well with hw_chanid */
+ ret = kstrtoul(chanid, 0, &hwid);
+ if (ret || hwid != fsl_chan->hw_chanid) {
+ dev_err(&pdev->dev, "%s,mismatch id/address!\n", txirq_name);
+ return -EINVAL;
+ }
+
+ fsl_chan->txirq = platform_get_irq_byname(pdev, txirq_name);
+ if (fsl_chan->txirq < 0) {
+ dev_err(&pdev->dev, "Can't get %s irq.\n", txirq_name);
+ return -EINVAL;
+ }
+
+ memcpy(fsl_chan->chan_name, txirq_name, strlen(txirq_name));
+
+ fsl_edma3_setup_regs(fsl_chan);
+
+ return 0;
+}
+
+static int fsl_edma3_request_chanirq(struct fsl_edma_chan *fsl_chan)
+{
+ struct fsl_edma3_engine *fsl_edma3 = to_fsl_edma3(fsl_chan->edma);
+ struct device *fsl_edma3_dev = fsl_edma3->fsl_edma.dma_dev.dev;
+ const char *txirq_name = fsl_chan->chan_name;
+ int ret;
+
+ pm_runtime_get_sync(fsl_chan->dev);
+
+ /* clear meaningless pending irq anyway */
+ if (edma_readl(&fsl_edma3->fsl_edma, fsl_chan->regs.intl))
+ edma_writel(&fsl_edma3->fsl_edma, 1, fsl_chan->regs.intl);
+
+ ret = devm_request_irq(fsl_edma3_dev, fsl_chan->txirq,
+ fsl_edma3_irq_handler, fsl_edma3->irqflag, txirq_name,
+ fsl_chan);
+ if (ret) {
+ dev_err(fsl_edma3_dev, "Can't register %s IRQ.\n",
+ txirq_name);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int fsl_edma3_free_chanirq(struct fsl_edma_chan *fsl_chan)
+{
+ struct fsl_edma3_engine *fsl_edma3 = to_fsl_edma3(fsl_chan->edma);
+ struct device *fsl_edma3_dev = fsl_edma3->fsl_edma.dma_dev.dev;
+ unsigned long flags;
+
+ devm_free_irq(fsl_edma3_dev, fsl_chan->txirq, fsl_chan);
+
+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+
+ fsl_chan->tcd_pool = NULL;
+
+ if (edma_readl(&fsl_edma3->fsl_edma, fsl_chan->regs.intl))
+ edma_writel(&fsl_edma3->fsl_edma, 1, fsl_chan->regs.intl);
+
+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+
+ pm_runtime_put_sync(fsl_chan->dev);
+
+ return 0;
+}
+
+static struct fsl_edma_drvdata imx8q_data = {
+ .version = v4,
+ .is_split = true,
+ .en_req = fsl_edma3_enable_request,
+ .dis_req = fsl_edma3_disable_request,
+ .request_irq = fsl_edma3_request_chanirq,
+ .free_irq = fsl_edma3_free_chanirq,
+};
+
+static const struct of_device_id fsl_edma3_dt_ids[] = {
+ { .compatible = "fsl,imx8qm-edma", .data = &imx8q_data},
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, fsl_edma3_dt_ids);
+
+static int fsl_edma3_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *of_id =
+ of_match_device(fsl_edma3_dt_ids, &pdev->dev);
+ struct device_node *np = pdev->dev.of_node;
+ struct fsl_edma3_engine *fsl_edma3;
+ struct fsl_edma_engine *fsl_edma;
+ const struct fsl_edma_drvdata *drvdata = NULL;
+ struct fsl_edma_chan *fsl_chan;
+ int len, chans;
+ int ret, i;
+
+ if (of_id)
+ drvdata = of_id->data;
+ if (!drvdata) {
+ dev_err(&pdev->dev, "unable to find driver data\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(np, "dma-channels", &chans);
+ if (ret) {
+ dev_err(&pdev->dev, "Can't get dma-channels.\n");
+ return ret;
+ }
+
+ len = sizeof(*fsl_edma3) + sizeof(*fsl_chan) * chans;
+ fsl_edma3 = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
+ if (!fsl_edma3)
+ return -ENOMEM;
+
+ /* Audio edma rx/tx channel shared interrupt */
+ if (of_property_read_bool(np, "shared-interrupt"))
+ fsl_edma3->irqflag = IRQF_SHARED;
+
+ fsl_edma = &fsl_edma3->fsl_edma;
+ fsl_edma->drvdata = drvdata;
+ fsl_edma->n_chans = chans;
+ mutex_init(&fsl_edma->fsl_edma_mutex);
+
+ INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+ struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+
+ fsl_chan->edma = fsl_edma;
+ fsl_chan->pm_state = RUNNING;
+ fsl_chan->idle = true;
+ fsl_chan->dma_dir = DMA_NONE;
+ fsl_chan->vchan.desc_free = fsl_edma_free_desc;
+
+ ret = fsl_edma3_parse_chanirq(pdev, fsl_chan, i);
+ if (ret)
+ return ret;
+
+ vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
+ }
+
+ dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
+ dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
+ dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
+
+ fsl_edma->dma_dev.dev = &pdev->dev;
+ fsl_edma->dma_dev.device_alloc_chan_resources
+ = fsl_edma_alloc_chan_resources;
+ fsl_edma->dma_dev.device_free_chan_resources
+ = fsl_edma_free_chan_resources;
+ fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
+ fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
+ fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
+ fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
+ fsl_edma->dma_dev.device_pause = fsl_edma_pause;
+ fsl_edma->dma_dev.device_resume = fsl_edma_resume;
+ fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
+ fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
+
+ fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
+ fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
+ fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) |
+ BIT(DMA_MEM_TO_DEV);
+
+ platform_set_drvdata(pdev, fsl_edma3);
+
+ ret = dma_async_device_register(&fsl_edma->dma_dev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Can't register Freescale eDMA engine. (%d)\n", ret);
+ return ret;
+ }
+
+ /* Attach power domains from dts for each dma chanel device */
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+ struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
+ const char *domn = "edma0-chan01";
+ struct device_link *link;
+ struct device *dev;
+
+ ret = of_property_read_string_index(np, "power-domain-names",
+ i, &domn);
+ if (ret) {
+ dev_err(dev, "parse domain names error.(%d)\n", ret);
+ ret = -EINVAL;
+ goto failed_after_register;
+ }
+
+ dev = dev_pm_domain_attach_by_name(&pdev->dev, domn);
+ if (IS_ERR_OR_NULL(dev)) {
+ if (PTR_ERR(dev) == -EPROBE_DEFER) {
+ ret = -EPROBE_DEFER;
+ goto failed_after_register;
+ }
+
+ dev_err(&pdev->dev, "edma channel attach failed.\n");
+ ret = -EINVAL;
+ goto failed_after_register;
+ }
+ link = device_link_add(&pdev->dev, dev, DL_FLAG_STATELESS |
+ DL_FLAG_PM_RUNTIME | DL_FLAG_RPM_ACTIVE);
+ if (IS_ERR(link)) {
+ dev_err(&pdev->dev, "Failed to add link to %s: %ld\n",
+ domn, PTR_ERR(link));
+ ret = -EINVAL;
+ goto failed_after_register;
+ }
+
+ fsl_chan->dev = dev;
+ /* clear meaningless pending irq anyway */
+ edma_writel(fsl_edma, 1, fsl_chan->regs.intl);
+ pm_runtime_put_sync(dev);
+ }
+
+ ret = of_dma_controller_register(np, fsl_edma3_xlate, fsl_edma);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Can't register Freescale eDMA of_dma. (%d)\n", ret);
+ goto failed_after_register;
+ }
+
+ pm_runtime_dont_use_autosuspend(&pdev->dev);
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+failed_after_register:
+ dma_async_device_unregister(&fsl_edma->dma_dev);
+ return ret;
+}
+
+static int fsl_edma3_remove(struct platform_device *pdev)
+{
+ struct fsl_edma3_engine *fsl_edma3 = platform_get_drvdata(pdev);
+ struct fsl_edma_engine *fsl_edma = &fsl_edma3->fsl_edma;
+ struct device_node *np = pdev->dev.of_node;
+
+ fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
+ of_dma_controller_free(np);
+ dma_async_device_unregister(&fsl_edma->dma_dev);
+
+ return 0;
+}
+
+static int fsl_edma3_suspend_late(struct device *dev)
+{
+ struct fsl_edma3_engine *fsl_edma3 = dev_get_drvdata(dev);
+ struct fsl_edma_engine *fsl_edma = &fsl_edma3->fsl_edma;
+ struct fsl_edma_chan *fsl_chan;
+ unsigned long flags;
+ int i;
+
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+ fsl_chan = &fsl_edma->chans[i];
+
+ if (pm_runtime_status_suspended(fsl_chan->dev))
+ continue;
+
+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+ /* Make sure chan is idle or will force disable. */
+ if (unlikely(!fsl_chan->idle)) {
+ dev_warn(dev, "WARN: There is non-idle channel.");
+ fsl_edma3_disable_request(fsl_chan);
+ }
+ /* Get the processed tcd number for resume back */
+ if (fsl_chan->edesc)
+ fsl_edma_get_realcnt(fsl_chan);
+
+ fsl_chan->pm_state = SUSPENDED;
+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+ }
+
+ return 0;
+}
+
+static int fsl_edma3_resume_early(struct device *dev)
+{
+ struct fsl_edma3_engine *fsl_edma3 = dev_get_drvdata(dev);
+ struct fsl_edma_engine *fsl_edma = &fsl_edma3->fsl_edma;
+ struct fsl_edma_chan *fsl_chan;
+ unsigned long flags;
+ int i;
+
+ for (i = 0; i < fsl_edma->n_chans; i++) {
+ fsl_chan = &fsl_edma->chans[i];
+
+ if (pm_runtime_status_suspended(fsl_chan->dev))
+ continue;
+
+ /* setup tcd before channel resume in case it's paused */
+ if (fsl_chan->edesc) {
+ u32 next = (fsl_chan->processed + 1) %
+ fsl_chan->edesc->n_tcds;
+
+ fsl_edma_set_tcd_regs(fsl_chan,
+ fsl_chan->edesc->tcd[next].vtcd);
+ }
+
+ spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
+ fsl_chan->pm_state = RUNNING;
+ spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
+ }
+
+ return 0;
+}
+
+/*
+ * eDMA provides the service to others, so it should be suspend late
+ * and resume early. When eDMA suspend, all of the clients should stop
+ * the DMA data transmission and let the channel idle.
+ */
+static const struct dev_pm_ops fsl_edma3_pm_ops = {
+ .suspend_late = fsl_edma3_suspend_late,
+ .resume_early = fsl_edma3_resume_early,
+};
+
+static struct platform_driver fsl_edma3_driver = {
+ .driver = {
+ .name = "imx8qm-edma",
+ .of_match_table = fsl_edma3_dt_ids,
+ .pm = &fsl_edma3_pm_ops,
+ },
+ .probe = fsl_edma3_probe,
+ .remove = fsl_edma3_remove,
+};
+
+static int __init fsl_edma3_init(void)
+{
+ return platform_driver_register(&fsl_edma3_driver);
+}
+subsys_initcall(fsl_edma3_init);
+
+static void __exit fsl_edma3_exit(void)
+{
+ platform_driver_unregister(&fsl_edma3_driver);
+}
+module_exit(fsl_edma3_exit);
+
+MODULE_ALIAS("platform:imx8qm-edma");
+MODULE_DESCRIPTION("NXP i.mx8qm/qxp eDMA engine driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (4 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 5/9] dmaengine: fsl-edma3: add fsl-edma3 driver Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-16 19:47 ` Rob Herring
2020-07-14 17:41 ` [PATCH v2 7/9] firmware: imx: scu-pd: correct dma resource Robin Gong
` (2 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
Add device binding doc for fsl-edma3 driver.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
.../devicetree/bindings/dma/nxp,fsl-edma3.yaml | 134 +++++++++++++++++++++
1 file changed, 134 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
diff --git a/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml b/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
new file mode 100644
index 00000000..ebdad90
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nxp,fsl-edma3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP eDMA3 Controller
+
+maintainers:
+ - Robin Gong <yibin.gong@nxp.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - fsl,imx8qm-edma # i.mx8qm/qxp
+
+ reg:
+ minItems: 2
+ maxItems: 32
+
+ interrupts:
+ minItems: 2
+ maxItems: 32
+
+ interrupt-names:
+ minItems: 2
+ maxItems: 32
+ items:
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
+
+ '#dma-cells':
+ const: 3
+ description: |
+ The 1st cell specifies the channel ID.
+
+ The 2nd cell specifies the channel priority.
+
+ The 3rd cell specifies the channel attributes:
+ bit0 transmit or receive.
+ 0 = transmit
+ 1 = receive
+ bit1 local or remote access.
+ 0 = local
+ 1 = remote
+ bit2 dualfifo case or not(only in Audio cyclic now).
+ 0 = not dual fifo case
+ 1 = dualfifo case.
+
+ dma-channels:
+ minimum: 2
+ maximum: 32
+
+ power-domains:
+ minItems: 2
+ maxItems: 32
+
+ power-domain-names:
+ minItems: 2
+ maxItems: 32
+ items:
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+ - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - '#dma-cells'
+ - dma-channels
+ - power-domains
+ - power-domain-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ edma2: dma-controller@5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
+ <0x5a290000 0x10000>, /* channel9 UART0 tx */
+ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
+ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
+ <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
+ <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
+ <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
+ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+ "edma2-chan10-rx", "edma2-chan11-tx",
+ "edma2-chan12-rx", "edma2-chan13-tx",
+ "edma2-chan14-rx", "edma2-chan15-tx";
+ power-domains = <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>;
+ power-domain-names = "edma2-chan8", "edma2-chan9",
+ "edma2-chan10", "edma2-chan11",
+ "edma2-chan12", "edma2-chan13",
+ "edma2-chan14", "edma2-chan15";
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml
2020-07-14 17:41 ` [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml Robin Gong
@ 2020-07-16 19:47 ` Rob Herring
2020-07-24 10:13 ` Robin Gong
0 siblings, 1 reply; 12+ messages in thread
From: Rob Herring @ 2020-07-16 19:47 UTC (permalink / raw)
To: Robin Gong
Cc: vkoul, shawnguo, s.hauer, festevam, catalin.marinas, will,
dan.j.williams, angelo, kernel, linux-imx, dmaengine, devicetree,
linux-kernel, linux-arm-kernel
On Wed, Jul 15, 2020 at 01:41:45AM +0800, Robin Gong wrote:
> Add device binding doc for fsl-edma3 driver.
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
> ---
> .../devicetree/bindings/dma/nxp,fsl-edma3.yaml | 134 +++++++++++++++++++++
> 1 file changed, 134 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml b/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
> new file mode 100644
> index 00000000..ebdad90
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/nxp,fsl-edma3.yaml
> @@ -0,0 +1,134 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/nxp,fsl-edma3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP eDMA3 Controller
> +
> +maintainers:
> + - Robin Gong <yibin.gong@nxp.com>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,imx8qm-edma # i.mx8qm/qxp
> +
> + reg:
> + minItems: 2
> + maxItems: 32
Needs some sort of description as to what each region is.
> +
> + interrupts:
> + minItems: 2
> + maxItems: 32
ditto
> +
> + interrupt-names:
> + minItems: 2
> + maxItems: 32
> + items:
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
What about interrupts 8-31? If you want a pattern for all entries, you
do:
items:
pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
(If 'items' is a schema instead of a list, then it applies to all
entries.)
What does edma[0-2] correspond to? The names should be local to the
instance.
Really, what's the point of names that just have the channel number in
them? The driver can create names dynamically if needed. We already have
properties to define how many channels and a mask of present channels.
> +
> + '#dma-cells':
> + const: 3
> + description: |
> + The 1st cell specifies the channel ID.
> +
> + The 2nd cell specifies the channel priority.
> +
> + The 3rd cell specifies the channel attributes:
> + bit0 transmit or receive.
> + 0 = transmit
> + 1 = receive
> + bit1 local or remote access.
> + 0 = local
> + 1 = remote
> + bit2 dualfifo case or not(only in Audio cyclic now).
> + 0 = not dual fifo case
> + 1 = dualfifo case.
> +
> + dma-channels:
> + minimum: 2
> + maximum: 32
> +
> + power-domains:
> + minItems: 2
> + maxItems: 32
> +
> + power-domain-names:
> + minItems: 2
> + maxItems: 32
> + items:
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
Again, why do you need names here?
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - '#dma-cells'
> + - dma-channels
> + - power-domains
> + - power-domain-names
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + edma2: dma-controller@5a1f0000 {
> + compatible = "fsl,imx8qm-edma";
> + reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
> + <0x5a290000 0x10000>, /* channel9 UART0 tx */
> + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
> + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
> + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
> + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
> + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
> + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
> + #dma-cells = <3>;
> + dma-channels = <8>;
> + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
> + "edma2-chan10-rx", "edma2-chan11-tx",
> + "edma2-chan12-rx", "edma2-chan13-tx",
> + "edma2-chan14-rx", "edma2-chan15-tx";
> + power-domains = <&pd IMX_SC_R_DMA_2_CH8>,
> + <&pd IMX_SC_R_DMA_2_CH9>,
> + <&pd IMX_SC_R_DMA_2_CH10>,
> + <&pd IMX_SC_R_DMA_2_CH11>,
> + <&pd IMX_SC_R_DMA_2_CH12>,
> + <&pd IMX_SC_R_DMA_2_CH13>,
> + <&pd IMX_SC_R_DMA_2_CH14>,
> + <&pd IMX_SC_R_DMA_2_CH15>;
> + power-domain-names = "edma2-chan8", "edma2-chan9",
> + "edma2-chan10", "edma2-chan11",
> + "edma2-chan12", "edma2-chan13",
> + "edma2-chan14", "edma2-chan15";
> + };
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml
2020-07-16 19:47 ` Rob Herring
@ 2020-07-24 10:13 ` Robin Gong
0 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-24 10:13 UTC (permalink / raw)
To: Rob Herring
Cc: vkoul, shawnguo, s.hauer, festevam, catalin.marinas, will,
dan.j.williams, angelo, kernel, dl-linux-imx, dmaengine,
devicetree, linux-kernel, linux-arm-kernel
On 2020/07/17 3:48 Rob Herring <robh@kernel.org> wrote:
> > +
> > + reg:
> > + minItems: 2
> > + maxItems: 32
>
> Needs some sort of description as to what each region is.
Okay, will add it in v3.
>
> > +
> > + interrupts:
> > + minItems: 2
> > + maxItems: 32
>
> ditto
Will add it in v3.
>
> > +
> > + interrupt-names:
> > + minItems: 2
> > + maxItems: 32
> > + items:
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
>
> What about interrupts 8-31? If you want a pattern for all entries, you
Here 8 lines matches with the 8 channel used in dts (same example as the
bottom of this yaml file below), otherwise, below warning comes out with
'make dt_binding_check' if I remove the above last line:
dma-controller@5a1f0000: interrupt-names: Additional items are not allowed ('edma2-chan15-tx' was unexpected)
Maybe there something I miss, please correct me if I'm wrong, thanks.
> do:
>
> items:
> pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])-tx|rx+$"
>
> (If 'items' is a schema instead of a list, then it applies to all
> entries.)
>
> What does edma[0-2] correspond to? The names should be local to the
> instance.
There are 3 edma controllers on i.mx8QXP/QM, [0-2] is controller index.
Clear controller index here may make dts readable since every edma channel
has unique register map, interrupt number, power domain.
>
> Really, what's the point of names that just have the channel number in them?
> The driver can create names dynamically if needed. We already have
> properties to define how many channels and a mask of present channels.
interrupt-names/power-domain-names here just for better readable in dts, besides, the clear interrupt name for every channel including edma controller
id which passed by dts could be used to register irq.
>
> > +
> > + '#dma-cells':
> > + const: 3
> > + description: |
> > + The 1st cell specifies the channel ID.
> > +
> > + The 2nd cell specifies the channel priority.
> > +
> > + The 3rd cell specifies the channel attributes:
> > + bit0 transmit or receive.
> > + 0 = transmit
> > + 1 = receive
> > + bit1 local or remote access.
> > + 0 = local
> > + 1 = remote
> > + bit2 dualfifo case or not(only in Audio cyclic now).
> > + 0 = not dual fifo case
> > + 1 = dualfifo case.
> > +
> > + dma-channels:
> > + minimum: 2
> > + maximum: 32
> > +
> > + power-domains:
> > + minItems: 2
> > + maxItems: 32
> > +
> > + power-domain-names:
> > + minItems: 2
> > + maxItems: 32
> > + items:
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
> > + - pattern: "^edma[0-2]-chan([0-9]|[1-2][0-9]|3[0-1])+$"
>
> Again, why do you need names here?
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - '#dma-cells'
> > + - dma-channels
> > + - power-domains
> > + - power-domain-names
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > + edma2: dma-controller@5a1f0000 {
> > + compatible = "fsl,imx8qm-edma";
> > + reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
> > + <0x5a290000 0x10000>, /* channel9 UART0 tx */
> > + <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
> > + <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
> > + <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
> > + <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
> > + <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
> > + <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
> > + #dma-cells = <3>;
> > + dma-channels = <8>;
> > + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
> > + "edma2-chan10-rx", "edma2-chan11-tx",
> > + "edma2-chan12-rx", "edma2-chan13-tx",
> > + "edma2-chan14-rx", "edma2-chan15-tx";
> > + power-domains = <&pd IMX_SC_R_DMA_2_CH8>,
> > + <&pd IMX_SC_R_DMA_2_CH9>,
> > + <&pd IMX_SC_R_DMA_2_CH10>,
> > + <&pd IMX_SC_R_DMA_2_CH11>,
> > + <&pd IMX_SC_R_DMA_2_CH12>,
> > + <&pd IMX_SC_R_DMA_2_CH13>,
> > + <&pd IMX_SC_R_DMA_2_CH14>,
> > + <&pd IMX_SC_R_DMA_2_CH15>;
> > + power-domain-names = "edma2-chan8", "edma2-chan9",
> > + "edma2-chan10", "edma2-chan11",
> > + "edma2-chan12", "edma2-chan13",
> > + "edma2-chan14", "edma2-chan15";
> > + };
> > --
> > 2.7.4
> >
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 7/9] firmware: imx: scu-pd: correct dma resource
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (5 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 6/9] dt-bindings: dma: add fsl-edma3 yaml Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 8/9] arm64: dts: imx8qxp: add edma2 Robin Gong
2020-07-14 17:41 ` [PATCH v2 9/9] arm64: defconfig: add CONFIG_FSL_EDMA3 Robin Gong
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
enlarge dma0/dma1 channel resource to 32 and split two parts of dma2 since
their resource id are not continouse.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
drivers/firmware/imx/scu-pd.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/imx/scu-pd.c b/drivers/firmware/imx/scu-pd.c
index af3d6d9..9818890 100644
--- a/drivers/firmware/imx/scu-pd.c
+++ b/drivers/firmware/imx/scu-pd.c
@@ -110,9 +110,10 @@ static const struct imx_sc_pd_range imx8qxp_scu_pd_ranges[] = {
{ "audio-pll1", IMX_SC_R_AUDIO_PLL_1, 1, false, 0 },
{ "audio-clk-0", IMX_SC_R_AUDIO_CLK_0, 1, false, 0 },
{ "audio-clk-1", IMX_SC_R_AUDIO_CLK_1, 1, false, 0 },
- { "dma0-ch", IMX_SC_R_DMA_0_CH0, 16, true, 0 },
- { "dma1-ch", IMX_SC_R_DMA_1_CH0, 16, true, 0 },
- { "dma2-ch", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
+ { "dma0-ch", IMX_SC_R_DMA_0_CH0, 32, true, 0 },
+ { "dma1-ch", IMX_SC_R_DMA_1_CH0, 32, true, 0 },
+ { "dma2-ch0", IMX_SC_R_DMA_2_CH0, 5, true, 0 },
+ { "dma2-ch1", IMX_SC_R_DMA_2_CH5, 27, true, 0 },
{ "asrc0", IMX_SC_R_ASRC_0, 1, false, 0 },
{ "asrc1", IMX_SC_R_ASRC_1, 1, false, 0 },
{ "esai0", IMX_SC_R_ESAI_0, 1, false, 0 },
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 8/9] arm64: dts: imx8qxp: add edma2
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (6 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 7/9] firmware: imx: scu-pd: correct dma resource Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
2020-07-14 17:41 ` [PATCH v2 9/9] arm64: defconfig: add CONFIG_FSL_EDMA3 Robin Gong
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
add edma2 on i.mx8qxp.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index e46faac..3f4fa59d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -300,6 +300,44 @@
status = "disabled";
};
+ edma2: dma-controller@5a1f0000 {
+ compatible = "fsl,imx8qm-edma";
+ reg = <0x5a280000 0x10000>, /* channel8 UART0 rx */
+ <0x5a290000 0x10000>, /* channel9 UART0 tx */
+ <0x5a2a0000 0x10000>, /* channel10 UART1 rx */
+ <0x5a2b0000 0x10000>, /* channel11 UART1 tx */
+ <0x5a2c0000 0x10000>, /* channel12 UART2 rx */
+ <0x5a2d0000 0x10000>, /* channel13 UART2 tx */
+ <0x5a2e0000 0x10000>, /* channel14 UART3 rx */
+ <0x5a2f0000 0x10000>; /* channel15 UART3 tx */
+ #dma-cells = <3>;
+ dma-channels = <8>;
+ interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "edma2-chan8-rx", "edma2-chan9-tx",
+ "edma2-chan10-rx", "edma2-chan11-tx",
+ "edma2-chan12-rx", "edma2-chan13-tx",
+ "edma2-chan14-rx", "edma2-chan15-tx";
+ power-domains = <&pd IMX_SC_R_DMA_2_CH8>,
+ <&pd IMX_SC_R_DMA_2_CH9>,
+ <&pd IMX_SC_R_DMA_2_CH10>,
+ <&pd IMX_SC_R_DMA_2_CH11>,
+ <&pd IMX_SC_R_DMA_2_CH12>,
+ <&pd IMX_SC_R_DMA_2_CH13>,
+ <&pd IMX_SC_R_DMA_2_CH14>,
+ <&pd IMX_SC_R_DMA_2_CH15>;
+ power-domain-names = "edma2-chan8", "edma2-chan9",
+ "edma2-chan10", "edma2-chan11",
+ "edma2-chan12", "edma2-chan13",
+ "edma2-chan14", "edma2-chan15";
+ };
+
adma_i2c0: i2c@5a800000 {
compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
reg = <0x5a800000 0x4000>;
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 9/9] arm64: defconfig: add CONFIG_FSL_EDMA3
2020-07-14 17:41 [PATCH v2 0/9] add fsl-edma3 support Robin Gong
` (7 preceding siblings ...)
2020-07-14 17:41 ` [PATCH v2 8/9] arm64: dts: imx8qxp: add edma2 Robin Gong
@ 2020-07-14 17:41 ` Robin Gong
8 siblings, 0 replies; 12+ messages in thread
From: Robin Gong @ 2020-07-14 17:41 UTC (permalink / raw)
To: vkoul, robh+dt, shawnguo, s.hauer, festevam, catalin.marinas,
will, dan.j.williams, angelo
Cc: kernel, linux-imx, dmaengine, devicetree, linux-kernel, linux-arm-kernel
Add CONFIG_FSL_EDMA3 for i.mx8qxp/i.mx8qm.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ae76fae..d786bd9 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -770,6 +770,7 @@ CONFIG_DMADEVICES=y
CONFIG_DMA_BCM2835=y
CONFIG_DMA_SUN6I=m
CONFIG_FSL_EDMA=y
+CONFIG_FSL_EDMA3=y
CONFIG_IMX_SDMA=y
CONFIG_K3_DMA=y
CONFIG_MV_XOR=y
--
2.7.4
^ permalink raw reply related [flat|nested] 12+ messages in thread