[PATCH v6] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue

[PATCH v6] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue

[EastL Lee]

This patch set adds document the devicetree bindings for MediaTek Command-Queue DMA controller,
and remove redundant queue structure.

hanges since v5:
- fix full name

hanges since v4:
- fix yaml & dma-mask code flow

hanges since v3:
- fix dt_binding_check errors

Changes since v2:
- add devicetree bindings for MediaTek Command-Queue DMA controller

Changes since v1:
- remove redundant queue structure
- fix wrong description and tags in the earlier patch
- add dma-channel-mask for DMA capability
- fix compatible for common

[PATCH v6 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings

[EastL Lee]

Document the devicetree bindings for MediaTek Command-Queue DMA controller
which could be found on MT6779 SoC or other similar Mediatek SoCs.

Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
---
 .../devicetree/bindings/dma/mtk-cqdma.yaml         | 113 +++++++++++++++++++++
 1 file changed, 113 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml

diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
new file mode 100644
index 0000000..83ed742
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Command-Queue DMA controller Device Tree Binding
+
+maintainers:
+  - EastL Lee <EastL.Lee@mediatek.com>
+
+description:
+  MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
+  is dedicated to memory-to-memory transfer through queue based
+  descriptor management.
+
+allOf:
+  - $ref: "dma-controller.yaml#"
+
+properties:
+  "#dma-cells":
+    minimum: 1
+    maximum: 255
+    description:
+      Used to provide DMA controller specific information.
+
+  compatible:
+    oneOf:
+      - const: mediatek,mt6765-cqdma
+      - const: mediatek,mt6779-cqdma
+
+  reg:
+    minItems: 1
+    maxItems: 5
+    description:
+        A base address of MediaTek Command-Queue DMA controller,
+        a channel will have a set of base address.
+
+  interrupts:
+    minItems: 1
+    maxItems: 5
+    description:
+        A interrupt number of MediaTek Command-Queue DMA controller,
+        one interrupt number per dma-channels.
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    const: cqdma
+
+  dma-channel-mask:
+    $ref: /schemas/types.yaml#definitions/uint32
+    description:
+       For DMA capability, We will know the addressing capability of
+       MediaTek Command-Queue DMA controller through dma-channel-mask.
+    items:
+      minItems: 1
+      maxItems: 63
+
+  dma-channels:
+    $ref: /schemas/types.yaml#definitions/uint32
+    description:
+      Number of DMA channels supported by MediaTek Command-Queue DMA
+      controller, support up to five.
+    items:
+      minItems: 1
+      maxItems: 5
+
+  dma-requests:
+    $ref: /schemas/types.yaml#definitions/uint32
+    description:
+      Number of DMA request (virtual channel) supported by MediaTek
+      Command-Queue DMA controller, support up to 32.
+    items:
+      minItems: 1
+      maxItems: 32
+
+required:
+  - "#dma-cells"
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - dma-channel-mask
+  - dma-channels
+  - dma-requests
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/irq.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/clock/mt6779-clk.h>
+    cqdma: dma-controller@10212000 {
+        compatible = "mediatek,mt6779-cqdma";
+        reg = <0x10212000 0x80>,
+            <0x10212080 0x80>,
+            <0x10212100 0x80>;
+        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
+            <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
+            <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+        clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
+        clock-names = "cqdma";
+        dma-channel-mask = <63>;
+        dma-channels = <3>;
+        dma-requests = <32>;
+        #dma-cells = <1>;
+    };
+
+...
-- 
1.9.1

[PATCH v6 3/4] dmaengine: mediatek-cqdma: add dma mask for capability

[EastL Lee]

This patch add dma mask for capability.

Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
---
 drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 905bbcb..1610632 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
  * @clk:                    The clock that device internal is using
  * @dma_requests:           The number of VCs the device supports to
  * @dma_channels:           The number of PCs the device supports to
+ * @dma_mask:               A mask for DMA capability
  * @vc:                     The pointer to all available VCs
  * @pc:                     The pointer to all the underlying PCs
  */
@@ -126,6 +127,7 @@ struct mtk_cqdma_device {
 
 	u32 dma_requests;
 	u32 dma_channels;
+	u32 dma_mask;
 	struct mtk_cqdma_vchan *vc;
 	struct mtk_cqdma_pchan **pc;
 };
@@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
 		cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
 	}
 
+	if (pdev->dev.of_node)
+		err = of_property_read_u32(pdev->dev.of_node,
+					   "dma-channel-mask",
+					   &cqdma->dma_mask);
+	if (err) {
+		dev_warn(&pdev->dev,
+			 "Using 0 as missing dma-channel-mask property\n");
+		cqdma->dma_mask = 0;
+	}
+
+	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) {
+		dev_warn(&pdev->dev, "DMA set mask failed\n");
+		return -EINVAL;
+	}
+
 	cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
 				 sizeof(*cqdma->pc), GFP_KERNEL);
 	if (!cqdma->pc)
-- 
1.9.1

[PATCH v6 4/4] dmaengine: mediatek-cqdma: fix compatible

[EastL Lee]

This patch adds mt6779 compatible.

Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
---
 drivers/dma/mediatek/mtk-cqdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
index 1610632..17b3ab9 100644
--- a/drivers/dma/mediatek/mtk-cqdma.c
+++ b/drivers/dma/mediatek/mtk-cqdma.c
@@ -547,6 +547,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
 
 static const struct of_device_id mtk_cqdma_match[] = {
 	{ .compatible = "mediatek,mt6765-cqdma" },
+	{ .compatible = "mediatek,mt6779-cqdma" },
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
-- 
1.9.1

Re: [PATCH v6 3/4] dmaengine: mediatek-cqdma: add dma mask for capability

[Matthias Brugger]

On 02/07/2020 09:06, EastL Lee wrote:
> This patch add dma mask for capability.
> 
> Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>  drivers/dma/mediatek/mtk-cqdma.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index 905bbcb..1610632 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
>   * @clk:                    The clock that device internal is using
>   * @dma_requests:           The number of VCs the device supports to
>   * @dma_channels:           The number of PCs the device supports to
> + * @dma_mask:               A mask for DMA capability
>   * @vc:                     The pointer to all available VCs
>   * @pc:                     The pointer to all the underlying PCs
>   */
> @@ -126,6 +127,7 @@ struct mtk_cqdma_device {
>  
>  	u32 dma_requests;
>  	u32 dma_channels;
> +	u32 dma_mask;
>  	struct mtk_cqdma_vchan *vc;
>  	struct mtk_cqdma_pchan **pc;
>  };
> @@ -607,6 +609,21 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
>  		cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
>  	}
>  
> +	if (pdev->dev.of_node)
> +		err = of_property_read_u32(pdev->dev.of_node,
> +					   "dma-channel-mask",
> +					   &cqdma->dma_mask);
> +	if (err) {
> +		dev_warn(&pdev->dev,
> +			 "Using 0 as missing dma-channel-mask property\n");
> +		cqdma->dma_mask = 0;
> +	}
> +
> +	if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(cqdma->dma_mask))) {
> +		dev_warn(&pdev->dev, "DMA set mask failed\n");
> +		return -EINVAL;
> +	}
> +
>  	cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
>  				 sizeof(*cqdma->pc), GFP_KERNEL);
>  	if (!cqdma->pc)
> 

Re: [PATCH v6 4/4] dmaengine: mediatek-cqdma: fix compatible

[Matthias Brugger]

On 02/07/2020 09:06, EastL Lee wrote:
> This patch adds mt6779 compatible.
> 
> Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>  drivers/dma/mediatek/mtk-cqdma.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index 1610632..17b3ab9 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -547,6 +547,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
>  
>  static const struct of_device_id mtk_cqdma_match[] = {
>  	{ .compatible = "mediatek,mt6765-cqdma" },
> +	{ .compatible = "mediatek,mt6779-cqdma" },
>  	{ /* sentinel */ }
>  };
>  MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
> 

Re: [PATCH v6 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings

[Rob Herring]

On Thu, Jul 02, 2020 at 03:06:01PM +0800, EastL Lee wrote:
> Document the devicetree bindings for MediaTek Command-Queue DMA controller
> which could be found on MT6779 SoC or other similar Mediatek SoCs.
> 
> Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
> ---
>  .../devicetree/bindings/dma/mtk-cqdma.yaml         | 113 +++++++++++++++++++++
>  1 file changed, 113 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> new file mode 100644
> index 0000000..83ed742
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> @@ -0,0 +1,113 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Command-Queue DMA controller Device Tree Binding
> +
> +maintainers:
> +  - EastL Lee <EastL.Lee@mediatek.com>
> +
> +description:
> +  MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> +  is dedicated to memory-to-memory transfer through queue based
> +  descriptor management.
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  "#dma-cells":
> +    minimum: 1
> +    maximum: 255
> +    description:
> +      Used to provide DMA controller specific information.

No, for a specific binding like this, it should be 1 defined value.

> +
> +  compatible:
> +    oneOf:
> +      - const: mediatek,mt6765-cqdma
> +      - const: mediatek,mt6779-cqdma
> +
> +  reg:
> +    minItems: 1
> +    maxItems: 5
> +    description:
> +        A base address of MediaTek Command-Queue DMA controller,
> +        a channel will have a set of base address.
> +
> +  interrupts:
> +    minItems: 1
> +    maxItems: 5
> +    description:
> +        A interrupt number of MediaTek Command-Queue DMA controller,
> +        one interrupt number per dma-channels.
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: cqdma
> +
> +  dma-channel-mask:
> +    $ref: /schemas/types.yaml#definitions/uint32

Alreay has a type, don't redefine it here.

> +    description:
> +       For DMA capability, We will know the addressing capability of
> +       MediaTek Command-Queue DMA controller through dma-channel-mask.

This sounds like the kernel's DMA masks which is not what this property 
is.

> +    items:
> +      minItems: 1
> +      maxItems: 63

An array of 63 elements?

I think you want:

minimum: 1
maximum: 63

Or:

enum: [ 1, 3, 7, 0xf, 0x1f, 0x3f ]

(Though if this works, then just 'dma-channels' is enough.)

> +
> +  dma-channels:
> +    $ref: /schemas/types.yaml#definitions/uint32
> +    description:
> +      Number of DMA channels supported by MediaTek Command-Queue DMA
> +      controller, support up to five.

Is it 5 or 6 channels? You're off by one somewhere.

> +    items:
> +      minItems: 1
> +      maxItems: 5
> +
> +  dma-requests:
> +    $ref: /schemas/types.yaml#definitions/uint32
> +    description:
> +      Number of DMA request (virtual channel) supported by MediaTek
> +      Command-Queue DMA controller, support up to 32.
> +    items:
> +      minItems: 1
> +      maxItems: 32

You are describing how many elements in an array and this is a scalar.

> +
> +required:
> +  - "#dma-cells"
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - dma-channel-mask
> +  - dma-channels
> +  - dma-requests
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/irq.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/mt6779-clk.h>
> +    cqdma: dma-controller@10212000 {
> +        compatible = "mediatek,mt6779-cqdma";
> +        reg = <0x10212000 0x80>,
> +            <0x10212080 0x80>,
> +            <0x10212100 0x80>;
> +        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> +            <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> +            <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> +        clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> +        clock-names = "cqdma";
> +        dma-channel-mask = <63>;
> +        dma-channels = <3>;
> +        dma-requests = <32>;
> +        #dma-cells = <1>;
> +    };
> +
> +...
> -- 
> 1.9.1

Re: [PATCH v6 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure

[Vinod Koul]

On 02-07-20, 15:06, EastL Lee wrote:

>  static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
>  					   dma_cookie_t cookie,
>  					   struct dma_tx_state *txstate)
>  {
> -	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> -	struct mtk_cqdma_vdesc *cvd;
> -	struct virt_dma_desc *vd;
> -	enum dma_status ret;
> -	unsigned long flags;
> -	size_t bytes = 0;
> -
> -	ret = dma_cookie_status(c, cookie, txstate);
> -	if (ret == DMA_COMPLETE || !txstate)
> -		return ret;
> -
> -	spin_lock_irqsave(&cvc->vc.lock, flags);
> -	vd = mtk_cqdma_find_active_desc(c, cookie);
> -	spin_unlock_irqrestore(&cvc->vc.lock, flags);
> -
> -	if (vd) {
> -		cvd = to_cqdma_vdesc(vd);
> -		bytes = cvd->residue;
> -	}
> -
> -	dma_set_residue(txstate, bytes);

any reason why you want to remove setting residue?

> -static void mtk_cqdma_free_active_desc(struct dma_chan *c)
> +static int mtk_cqdma_terminate_all(struct dma_chan *c)
>  {
>  	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> -	bool sync_needed = false;
> +	struct virt_dma_chan *vc = to_virt_chan(c);
>  	unsigned long pc_flags;
>  	unsigned long vc_flags;
> +	LIST_HEAD(head);
> +
> +	/* wait for the VC to be inactive  */
> +	if (!wait_for_completion_timeout(&cvc->cmp, msecs_to_jiffies(3000)))
> +		return -EAGAIN;
>  
>  	/* acquire PC's lock first due to lock dependency in dma ISR */
>  	spin_lock_irqsave(&cvc->pc->lock, pc_flags);
>  	spin_lock_irqsave(&cvc->vc.lock, vc_flags);
>  
> -	/* synchronization is required if this VC is active */
> -	if (mtk_cqdma_is_vchan_active(cvc)) {
> -		cvc->issue_synchronize = true;
> -		sync_needed = true;
> -	}
> +	/* get VDs from lists */
> +	vchan_get_all_descriptors(vc, &head);
> +
> +	/* free all the VDs */
> +	vchan_dma_desc_free_list(vc, &head);
>  
>  	spin_unlock_irqrestore(&cvc->vc.lock, vc_flags);
>  	spin_unlock_irqrestore(&cvc->pc->lock, pc_flags);

Good cleanup, do you need both these locks?
-- 
~Vinod

Re: [PATCH v6 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings

[EastL]

On Thu, 2020-07-09 at 14:59 -0600, Rob Herring wrote:
> On Thu, Jul 02, 2020 at 03:06:01PM +0800, EastL Lee wrote:
> > Document the devicetree bindings for MediaTek Command-Queue DMA controller
> > which could be found on MT6779 SoC or other similar Mediatek SoCs.
> > 
> > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
> > ---
> >  .../devicetree/bindings/dma/mtk-cqdma.yaml         | 113 +++++++++++++++++++++
> >  1 file changed, 113 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > new file mode 100644
> > index 0000000..83ed742
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > @@ -0,0 +1,113 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/dma/mtk-cqdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!1P_if3RiZOVpzN8n4EQI0IxZq0d07UksSgeHYA0h6HLylU9l4pu2eggq7eeVsF2H$ 
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1P_if3RiZOVpzN8n4EQI0IxZq0d07UksSgeHYA0h6HLylU9l4pu2eggq7ZMPow23$ 
> > +
> > +title: MediaTek Command-Queue DMA controller Device Tree Binding
> > +
> > +maintainers:
> > +  - EastL Lee <EastL.Lee@mediatek.com>
> > +
> > +description:
> > +  MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> > +  is dedicated to memory-to-memory transfer through queue based
> > +  descriptor management.
> > +
> > +allOf:
> > +  - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > +  "#dma-cells":
> > +    minimum: 1
> > +    maximum: 255
> > +    description:
> > +      Used to provide DMA controller specific information.
> 
> No, for a specific binding like this, it should be 1 defined value.
OK.I'll fix it to const 1
> 
> > +
> > +  compatible:
> > +    oneOf:
> > +      - const: mediatek,mt6765-cqdma
> > +      - const: mediatek,mt6779-cqdma
> > +
> > +  reg:
> > +    minItems: 1
> > +    maxItems: 5
> > +    description:
> > +        A base address of MediaTek Command-Queue DMA controller,
> > +        a channel will have a set of base address.
> > +
> > +  interrupts:
> > +    minItems: 1
> > +    maxItems: 5
> > +    description:
> > +        A interrupt number of MediaTek Command-Queue DMA controller,
> > +        one interrupt number per dma-channels.
> > +
> > +  clocks:
> > +    maxItems: 1
> > +
> > +  clock-names:
> > +    const: cqdma
> > +
> > +  dma-channel-mask:
> > +    $ref: /schemas/types.yaml#definitions/uint32
> 
> Alreay has a type, don't redefine it here.
OK
> 
> > +    description:
> > +       For DMA capability, We will know the addressing capability of
> > +       MediaTek Command-Queue DMA controller through dma-channel-mask.
> 
> This sounds like the kernel's DMA masks which is not what this property 
> is.
Yes, this is for kernel's DMA mask.
Do I need to declare this member again?
> 
> > +    items:
> > +      minItems: 1
> > +      maxItems: 63
> 
> An array of 63 elements?
> 
> I think you want:
> 
> minimum: 1
> maximum: 63
> 
> Or:
> 
> enum: [ 1, 3, 7, 0xf, 0x1f, 0x3f ]
> 
> (Though if this works, then just 'dma-channels' is enough.)
> 
> > +
> > +  dma-channels:
> > +    $ref: /schemas/types.yaml#definitions/uint32
> > +    description:
> > +      Number of DMA channels supported by MediaTek Command-Queue DMA
> > +      controller, support up to five.
> 
> Is it 5 or 6 channels? You're off by one somewhere.
Currently chip CQDMA only has three channels at most, I'll fix it to
maxnum 3
> > +    items:
> > +      minItems: 1
> > +      maxItems: 5
> > +
> > +  dma-requests:
> > +    $ref: /schemas/types.yaml#definitions/uint32
> > +    description:
> > +      Number of DMA request (virtual channel) supported by MediaTek
> > +      Command-Queue DMA controller, support up to 32.
> > +    items:
> > +      minItems: 1
> > +      maxItems: 32
> 
> You are describing how many elements in an array and this is a scalar.
OK I;ll fix to minnum & maxnum
> 
> > +
> > +required:
> > +  - "#dma-cells"
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - clocks
> > +  - clock-names
> > +  - dma-channel-mask
> > +  - dma-channels
> > +  - dma-requests
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/irq.h>
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/clock/mt6779-clk.h>
> > +    cqdma: dma-controller@10212000 {
> > +        compatible = "mediatek,mt6779-cqdma";
> > +        reg = <0x10212000 0x80>,
> > +            <0x10212080 0x80>,
> > +            <0x10212100 0x80>;
> > +        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> > +            <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> > +            <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> > +        clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> > +        clock-names = "cqdma";
> > +        dma-channel-mask = <63>;
> > +        dma-channels = <3>;
> > +        dma-requests = <32>;
> > +        #dma-cells = <1>;
> > +    };
> > +
> > +...
> > -- 
> > 1.9.1

Re: [PATCH v6 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure

[EastL]

On Wed, 2020-07-15 at 11:49 +0530, Vinod Koul wrote:
> On 02-07-20, 15:06, EastL Lee wrote:
> 
> >  static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
> >  					   dma_cookie_t cookie,
> >  					   struct dma_tx_state *txstate)
> >  {
> > -	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> > -	struct mtk_cqdma_vdesc *cvd;
> > -	struct virt_dma_desc *vd;
> > -	enum dma_status ret;
> > -	unsigned long flags;
> > -	size_t bytes = 0;
> > -
> > -	ret = dma_cookie_status(c, cookie, txstate);
> > -	if (ret == DMA_COMPLETE || !txstate)
> > -		return ret;
> > -
> > -	spin_lock_irqsave(&cvc->vc.lock, flags);
> > -	vd = mtk_cqdma_find_active_desc(c, cookie);
> > -	spin_unlock_irqrestore(&cvc->vc.lock, flags);
> > -
> > -	if (vd) {
> > -		cvd = to_cqdma_vdesc(vd);
> > -		bytes = cvd->residue;
> > -	}
> > -
> > -	dma_set_residue(txstate, bytes);
> 
> any reason why you want to remove setting residue?
Because Mediatek CQDMA HW can't support residue.
> 
> > -static void mtk_cqdma_free_active_desc(struct dma_chan *c)
> > +static int mtk_cqdma_terminate_all(struct dma_chan *c)
> >  {
> >  	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> > -	bool sync_needed = false;
> > +	struct virt_dma_chan *vc = to_virt_chan(c);
> >  	unsigned long pc_flags;
> >  	unsigned long vc_flags;
> > +	LIST_HEAD(head);
> > +
> > +	/* wait for the VC to be inactive  */
> > +	if (!wait_for_completion_timeout(&cvc->cmp, msecs_to_jiffies(3000)))
> > +		return -EAGAIN;
> >  
> >  	/* acquire PC's lock first due to lock dependency in dma ISR */
> >  	spin_lock_irqsave(&cvc->pc->lock, pc_flags);
> >  	spin_lock_irqsave(&cvc->vc.lock, vc_flags);
> >  
> > -	/* synchronization is required if this VC is active */
> > -	if (mtk_cqdma_is_vchan_active(cvc)) {
> > -		cvc->issue_synchronize = true;
> > -		sync_needed = true;
> > -	}
> > +	/* get VDs from lists */
> > +	vchan_get_all_descriptors(vc, &head);
> > +
> > +	/* free all the VDs */
> > +	vchan_dma_desc_free_list(vc, &head);
> >  
> >  	spin_unlock_irqrestore(&cvc->vc.lock, vc_flags);
> >  	spin_unlock_irqrestore(&cvc->pc->lock, pc_flags);
> 
> Good cleanup, do you need both these locks?
Yes, because we will have multiple vc to pc, it will need both lock.

Re: [PATCH v6 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure

[Vinod Koul]

On 23-07-20, 10:34, EastL wrote:
> On Wed, 2020-07-15 at 11:49 +0530, Vinod Koul wrote:
> > On 02-07-20, 15:06, EastL Lee wrote:
> > 
> > >  static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
> > >  					   dma_cookie_t cookie,
> > >  					   struct dma_tx_state *txstate)
> > >  {
> > > -	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> > > -	struct mtk_cqdma_vdesc *cvd;
> > > -	struct virt_dma_desc *vd;
> > > -	enum dma_status ret;
> > > -	unsigned long flags;
> > > -	size_t bytes = 0;
> > > -
> > > -	ret = dma_cookie_status(c, cookie, txstate);
> > > -	if (ret == DMA_COMPLETE || !txstate)
> > > -		return ret;
> > > -
> > > -	spin_lock_irqsave(&cvc->vc.lock, flags);
> > > -	vd = mtk_cqdma_find_active_desc(c, cookie);
> > > -	spin_unlock_irqrestore(&cvc->vc.lock, flags);
> > > -
> > > -	if (vd) {
> > > -		cvd = to_cqdma_vdesc(vd);
> > > -		bytes = cvd->residue;
> > > -	}
> > > -
> > > -	dma_set_residue(txstate, bytes);
> > 
> > any reason why you want to remove setting residue?
> Because Mediatek CQDMA HW can't support residue.

And previously it did?
-- 
~Vinod

Re: [PATCH v6 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure

[EastL]

On Mon, 2020-07-27 at 15:14 +0530, Vinod Koul wrote:
> On 23-07-20, 10:34, EastL wrote:
> > On Wed, 2020-07-15 at 11:49 +0530, Vinod Koul wrote:
> > > On 02-07-20, 15:06, EastL Lee wrote:
> > > 
> > > >  static enum dma_status mtk_cqdma_tx_status(struct dma_chan *c,
> > > >  					   dma_cookie_t cookie,
> > > >  					   struct dma_tx_state *txstate)
> > > >  {
> > > > -	struct mtk_cqdma_vchan *cvc = to_cqdma_vchan(c);
> > > > -	struct mtk_cqdma_vdesc *cvd;
> > > > -	struct virt_dma_desc *vd;
> > > > -	enum dma_status ret;
> > > > -	unsigned long flags;
> > > > -	size_t bytes = 0;
> > > > -
> > > > -	ret = dma_cookie_status(c, cookie, txstate);
> > > > -	if (ret == DMA_COMPLETE || !txstate)
> > > > -		return ret;
> > > > -
> > > > -	spin_lock_irqsave(&cvc->vc.lock, flags);
> > > > -	vd = mtk_cqdma_find_active_desc(c, cookie);
> > > > -	spin_unlock_irqrestore(&cvc->vc.lock, flags);
> > > > -
> > > > -	if (vd) {
> > > > -		cvd = to_cqdma_vdesc(vd);
> > > > -		bytes = cvd->residue;
> > > > -	}
> > > > -
> > > > -	dma_set_residue(txstate, bytes);
> > > 
> > > any reason why you want to remove setting residue?
> > Because Mediatek CQDMA HW can't support residue.
> 
> And previously it did?
No, It was calculated by sw before.
We found that the residue was not necessary, so we removed it.