From: EastL <EastL.Lee@mediatek.com>
To: Rob Herring <robh@kernel.org>
Cc: Sean Wang <sean.wang@mediatek.com>, <vkoul@kernel.org>,
<mark.rutland@arm.com>, <matthias.bgg@gmail.com>,
<dmaengine@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<devicetree@vger.kernel.org>, <wsd_upstream@mediatek.com>,
<cc.hwang@mediatek.com>
Subject: Re: [PATCH v7 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings
Date: Fri, 4 Dec 2020 15:17:44 +0800 [thread overview]
Message-ID: <1607066264.18639.3.camel@mtkswgap22> (raw)
In-Reply-To: <20200818164718.GB3596085@bogus>
sorry for the delayed response.
On Tue, 2020-08-18 at 10:47 -0600, Rob Herring wrote:
> On Tue, Aug 18, 2020 at 11:03:51AM +0800, EastL Lee wrote:
> > Document the devicetree bindings for MediaTek Command-Queue DMA controller
> > which could be found on MT6779 SoC or other similar Mediatek SoCs.
> >
> > Signed-off-by: EastL Lee <EastL.Lee@mediatek.com>
> > ---
> > .../devicetree/bindings/dma/mtk-cqdma.yaml | 98 ++++++++++++++++++++++
> > 1 file changed, 98 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > new file mode 100644
> > index 0000000..fe03081
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/mtk-cqdma.yaml
> > @@ -0,0 +1,98 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/mtk-cqdma.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: MediaTek Command-Queue DMA controller Device Tree Binding
> > +
> > +maintainers:
> > + - EastL Lee <EastL.Lee@mediatek.com>
> > +
> > +description:
> > + MediaTek Command-Queue DMA controller (CQDMA) on Mediatek SoC
> > + is dedicated to memory-to-memory transfer through queue based
> > + descriptor management.
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - const: mediatek,mt6765-cqdma
> > + - const: mediatek,mt6779-cqdma
>
> Use enum instead of oneOf+const.
OK
>
> > +
> > + reg:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A base address of MediaTek Command-Queue DMA controller,
> > + a channel will have a set of base address.
> > +
> > + interrupts:
> > + minItems: 1
> > + maxItems: 5
> > + description:
> > + A interrupt number of MediaTek Command-Queue DMA controller,
> > + one interrupt number per dma-channels.
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: cqdma
> > +
> > + dma-channels:
> > + $ref: /schemas/types.yaml#definitions/uint32
>
> Common properties already have a type definition.
OK I'll remove
>
> > + description:
> > + Number of DMA channels supported by MediaTek Command-Queue DMA
> > + controller, support up to five.
> > + items:
>
> Not an array, so drop 'items'.
OK
>
> > + minimum: 1
> > + maximum: 5
> > +
> > + dma-requests:
> > + $ref: /schemas/types.yaml#definitions/uint32
> > + description:
> > + Number of DMA request (virtual channel) supported by MediaTek
> > + Command-Queue DMA controller, support up to 32.
> > + items:
> > + minimum: 1
> > + maximum: 32
>
> Same issues here.
OK
>
> > +
> > +required:
> > + - "#dma-cells"
> > + - compatible
> > + - reg
> > + - interrupts
> > + - clocks
> > + - clock-names
> > + - dma-channel-mask
>
> Need to list in properties to fix the check error:
>
> dma-channel-mask: true
OK
>
> > + - dma-channels
> > + - dma-requests
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/mt6779-clk.h>
> > + cqdma: dma-controller@10212000 {
> > + compatible = "mediatek,mt6779-cqdma";
> > + reg = <0x10212000 0x80>,
> > + <0x10212080 0x80>,
> > + <0x10212100 0x80>;
> > + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&infracfg_ao CLK_INFRA_CQ_DMA>;
> > + clock-names = "cqdma";
> > + dma-channel-mask = <0x3f>;
> > + dma-channels = <3>;
> > + dma-requests = <32>;
> > + #dma-cells = <1>;
> > + };
> > +
> > +...
> > --
> > 1.9.1
next prev parent reply other threads:[~2020-12-04 7:18 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-18 3:03 [PATCH v7] dmaengine: mediatek-cqdma: add dt-bindings and remove redundant queue EastL Lee
2020-08-18 3:03 ` [PATCH v7 1/4] dt-bindings: dmaengine: Add MediaTek Command-Queue DMA controller bindings EastL Lee
2020-08-18 16:43 ` Rob Herring
2020-08-18 16:47 ` Rob Herring
2020-12-04 7:17 ` EastL [this message]
2020-08-18 3:03 ` [PATCH v7 2/4] dmaengine: mediatek-cqdma: remove redundant queue structure EastL Lee
2020-08-18 3:03 ` [PATCH v7 3/4] dmaengine: mediatek-cqdma: add dma mask for capability EastL Lee
2020-08-18 3:03 ` [PATCH v7 4/4] dmaengine: mediatek-cqdma: fix compatible EastL Lee
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