From: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
To: <vkoul@kernel.org>, <robh+dt@kernel.org>, <michal.simek@xilinx.com>
Cc: <dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <git@xilinx.com>,
Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Subject: [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property
Date: Fri, 9 Apr 2021 23:26:00 +0530 [thread overview]
Message-ID: <1617990965-35337-3-git-send-email-radhey.shyam.pandey@xilinx.com> (raw)
In-Reply-To: <1617990965-35337-1-git-send-email-radhey.shyam.pandey@xilinx.com>
Add an optional AXI DMA property 'xlnx,irq-delay'. It specifies interrupt
timeout value and causes the DMA engine to generate an interrupt after the
delay time period has expired. Timer begins counting at the end of a packet
and resets with receipt of a new packet or a timeout event occurs.
This property is useful when AXI DMA is connected to the streaming IP i.e
axiethernet where inter packet latency is critical while still taking the
benefit of interrupt coalescing.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
---
Changes for v2:
- New patch. Introduce xlnx,irq-delay property for low latency usecases
---
Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
index f5f23a4a4467..96009ced7b29 100644
--- a/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
+++ b/Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
@@ -50,7 +50,9 @@ Optional properties for AXI DMA and MCDMA:
is missing or invalid then the default value 23 is used. This is the
maximum value that is supported by all IP versions.
- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP.
-
+- xlnx,irq-delay: Tells the interrupt delay timeout value. Valid range is from
+ 0-255. Setting this value to zero disables the delay timer interrupt.
+ 1 timeout interval = 125 * clock period of SG clock.
Optional properties for VDMA:
- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
--
2.7.4
next prev parent reply other threads:[~2021-04-09 17:57 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-09 17:55 [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Radhey Shyam Pandey
2021-04-09 17:55 ` [RFC v2 PATCH 1/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,axistream-connected property Radhey Shyam Pandey
2021-04-12 18:25 ` Rob Herring
2021-04-09 17:56 ` Radhey Shyam Pandey [this message]
2021-04-12 18:25 ` [RFC v2 PATCH 2/7] dt-bindings: dmaengine: xilinx_dma: Add xlnx,irq-delay property Rob Herring
2021-04-09 17:56 ` [RFC v2 PATCH 3/7] dmaengine: xilinx_dma: Pass AXI4-Stream control words to dma client Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 4/7] dmaengine: xilinx_dma: Increase AXI DMA transaction segment count Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 5/7] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Radhey Shyam Pandey
2021-04-15 7:08 ` Lars-Peter Clausen
2021-06-11 16:16 ` Radhey Shyam Pandey
2021-04-15 7:26 ` Lars-Peter Clausen
2021-06-11 18:58 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 6/7] dmaengine: xilinx_dma: Use tasklet_hi_schedule for timing critical usecase Radhey Shyam Pandey
2021-04-15 7:10 ` Lars-Peter Clausen
2021-06-11 18:30 ` Radhey Shyam Pandey
2021-04-09 17:56 ` [RFC v2 PATCH 7/7] dmaengine: xilinx_dma: Program interrupt delay timeout Radhey Shyam Pandey
2021-04-15 7:33 ` Lars-Peter Clausen
2021-06-11 19:33 ` Radhey Shyam Pandey
2021-04-15 7:06 ` [RFC v2 PATCH 0/7] Xilinx DMA enhancements and optimization Lars-Peter Clausen
2021-06-11 16:13 ` Radhey Shyam Pandey
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