dmaengine Archive on lore.kernel.org
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From: Vinod Koul <vkoul@kernel.org>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: dmaengine@vger.kernel.org, Dan Williams <dan.j.williams@intel.com>
Subject: Re: [PATCH v1] dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width"
Date: Mon, 24 Jun 2019 17:30:02 +0530
Message-ID: <20190624120002.GA2962@vkoul-mobl> (raw)
In-Reply-To: <20190613133232.49971-1-andriy.shevchenko@linux.intel.com>

On 13-06-19, 16:32, Andy Shevchenko wrote:
> The commit
> 
>   080edf75d337 ("dmaengine: hsu: set HSU_CH_MTSR to memory width")
> 
> has been mistakenly submitted. The further investigations show that
> the original code does better job since the memory side transfer size
> has never been configured by DMA users.
> 
> As per latest revision of documentation: "Channel minimum transfer size
> (CHnMTSR)... For IOSF UART, maximum value that can be programmed is 64 and
> minimum value that can be programmed is 1."

Applied, thanks

-- 
~Vinod

      reply index

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-13 13:32 Andy Shevchenko
2019-06-24 12:00 ` Vinod Koul [this message]

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