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* [bug report] dmaengine: axi-dmac: Add support for interleaved cyclic transfers
@ 2019-06-24 12:13 Dan Carpenter
  0 siblings, 0 replies; only message in thread
From: Dan Carpenter @ 2019-06-24 12:13 UTC (permalink / raw)
  To: dragos.bogdan; +Cc: dmaengine

Hello Dragos Bogdan,

The patch 8add6cce9848: "dmaengine: axi-dmac: Add support for
interleaved cyclic transfers" from May 16, 2019, leads to the
following static checker warning:

	drivers/dma/dma-axi-dmac.c:666 axi_dmac_prep_interleaved()
	warn: bit shifter 'DMA_CYCLIC' used for logical '&'

   658          if (chan->hw_2d) {
   659                  desc->sg[0].x_len = xt->sgl[0].size;
   660                  desc->sg[0].y_len = xt->numf;
   661          } else {
   662                  desc->sg[0].x_len = xt->sgl[0].size * xt->numf;
   663                  desc->sg[0].y_len = 1;
   664          }
   666          if (flags & DMA_CYCLIC)
   667                  desc->cyclic = true;

This won't work.  I think you have to use dma_has_cap() or test_bit() or
something.  Or you could do:

	if (flags & (1 << DMA_CYCLIC)) {

DMA_CYCLIC is 0xb so this will return true for a bunch of stuff when it

   669          return vchan_tx_prep(&chan->vchan, &desc->vdesc, flags);
   670  }

dan carpenter

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2019-06-24 12:13 [bug report] dmaengine: axi-dmac: Add support for interleaved cyclic transfers Dan Carpenter

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