Re: [PATCH v4 01/15] bindings: soc: ti: add documentation for k3 ringacc

[Vinod Koul <vkoul@kernel.org>]

On 01-11-19, 10:41, Peter Ujfalusi wrote:
> From: Grygorii Strashko <grygorii.strashko@ti.com>
> 
> The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
> enable straightforward passing of work between a producer and a consumer.
> There is one RINGACC module per NAVSS on TI AM65x and j721e.
> 
> This patch introduces RINGACC device tree bindings.
> 
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
>  .../devicetree/bindings/soc/ti/k3-ringacc.txt | 59 +++++++++++++++++++
>  1 file changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt
> 
> diff --git a/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt
> new file mode 100644
> index 000000000000..86954cf4fa99
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/ti/k3-ringacc.txt
> @@ -0,0 +1,59 @@
> +* Texas Instruments K3 NavigatorSS Ring Accelerator
> +
> +The Ring Accelerator (RA) is a machine which converts read/write accesses
> +from/to a constant address into corresponding read/write accesses from/to a
> +circular data structure in memory. The RA eliminates the need for each DMA
> +controller which needs to access ring elements from having to know the current
> +state of the ring (base address, current offset). The DMA controller
> +performs a read or write access to a specific address range (which maps to the
> +source interface on the RA) and the RA replaces the address for the transaction
> +with a new address which corresponds to the head or tail element of the ring
> +(head for reads, tail for writes).
> +
> +The Ring Accelerator is a hardware module that is responsible for accelerating
> +management of the packet queues. The K3 SoCs can have more than one RA instances
> +
> +Required properties:
> +- compatible	: Must be "ti,am654-navss-ringacc";
> +- reg		: Should contain register location and length of the following
> +		  named register regions.
> +- reg-names	: should be
> +		  "rt" - The RA Ring Real-time Control/Status Registers
> +		  "fifos" - The RA Queues Registers
> +		  "proxy_gcfg" - The RA Proxy Global Config Registers
> +		  "proxy_target" - The RA Proxy Datapath Registers
> +- ti,num-rings	: Number of rings supported by RA
> +- ti,sci-rm-range-gp-rings : TI-SCI RM subtype for GP ring range
> +- ti,sci	: phandle on TI-SCI compatible System controller node
> +- ti,sci-dev-id	: TI-SCI device id
> +- msi-parent	: phandle for "ti,sci-inta" interrupt controller
> +
> +Optional properties:
> + -- ti,dma-ring-reset-quirk : enable ringacc / udma ring state interoperability
> +		  issue software w/a
> +
> +Example:
> +
> +ringacc: ringacc@3c000000 {
> +	compatible = "ti,am654-navss-ringacc";
> +	reg =	<0x0 0x3c000000 0x0 0x400000>,
> +		<0x0 0x38000000 0x0 0x400000>,
> +		<0x0 0x31120000 0x0 0x100>,
> +		<0x0 0x33000000 0x0 0x40000>;
> +	reg-names = "rt", "fifos",
> +		    "proxy_gcfg", "proxy_target";
> +	ti,num-rings = <818>;
> +	ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
> +	ti,dma-ring-reset-quirk;
> +	ti,sci = <&dmsc>;
> +	ti,sci-dev-id = <187>;

why do we need dev-id for? doesn't phandle the line above help?

-- 
~Vinod