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From: Dmitry Osipenko <digetx@gmail.com>
To: "Laxman Dewangan" <ldewangan@nvidia.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Michał Mirosław" <mirq-linux@rere.qmqm.pl>
Cc: dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH v7 15/19] dmaengine: tegra-apb: Clean up suspend-resume
Date: Mon,  3 Feb 2020 01:28:50 +0300
Message-ID: <20200202222854.18409-16-digetx@gmail.com> (raw)
In-Reply-To: <20200202222854.18409-1-digetx@gmail.com>

It is enough to check whether hardware is busy on suspend and to reset
it across of suspend-resume because:

  1. Channel's configuration is fully re-programmed on each DMA
     transfer anyways.

  2. Context save-restore of an active channel won't end up well without
     pausing transfer prior to the context's saving, but note that every
     channel shall be idling at the time of suspend, so save-restore is
     not needed at all.

  3. The only case where context save-restore may be useful is when
     channel is in a paused state during suspend. But channel's pausing
     could be supported only on Tegra114+ and this functionality wasn't
     implemented by the driver for years now because there is no need for
     it in upstream kernel.

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 drivers/dma/tegra20-apb-dma.c | 136 +++++++++++++++++-----------------
 1 file changed, 69 insertions(+), 67 deletions(-)

diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c
index 92535b962e64..db726e635048 100644
--- a/drivers/dma/tegra20-apb-dma.c
+++ b/drivers/dma/tegra20-apb-dma.c
@@ -221,9 +221,6 @@ struct tegra_dma {
 	 */
 	u32				global_pause_count;
 
-	/* Some register need to be cache before suspend */
-	u32				reg_gen;
-
 	/* Last member of the structure */
 	struct tegra_dma_channel channels[0];
 };
@@ -1389,6 +1386,36 @@ static const struct tegra_dma_chip_data tegra148_dma_chip_data = {
 	.support_separate_wcount_reg = true,
 };
 
+static int tegra_dma_init_hw(struct tegra_dma *tdma)
+{
+	int err;
+
+	err = reset_control_assert(tdma->rst);
+	if (err) {
+		dev_err(tdma->dev, "failed to assert reset: %d\n", err);
+		return err;
+	}
+
+	err = clk_enable(tdma->dma_clk);
+	if (err) {
+		dev_err(tdma->dev, "failed to enable clk: %d\n", err);
+		return err;
+	}
+
+	/* reset DMA controller */
+	udelay(2);
+	reset_control_deassert(tdma->rst);
+
+	/* enable global DMA registers */
+	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
+	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
+	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFF);
+
+	clk_disable(tdma->dma_clk);
+
+	return 0;
+}
+
 static int tegra_dma_probe(struct platform_device *pdev)
 {
 	const struct tegra_dma_chip_data *cdata;
@@ -1430,25 +1457,13 @@ static int tegra_dma_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	ret = tegra_dma_init_hw(tdma);
+	if (ret)
+		goto err_clk_unprepare;
+
 	pm_runtime_irq_safe(&pdev->dev);
 	pm_runtime_enable(&pdev->dev);
 
-	ret = pm_runtime_get_sync(&pdev->dev);
-	if (ret < 0)
-		goto err_pm_disable;
-
-	/* Reset DMA controller */
-	reset_control_assert(tdma->rst);
-	udelay(2);
-	reset_control_deassert(tdma->rst);
-
-	/* Enable global DMA registers */
-	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);
-	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
-	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
-
-	pm_runtime_put(&pdev->dev);
-
 	INIT_LIST_HEAD(&tdma->dma_dev.channels);
 	for (i = 0; i < cdata->nr_channels; i++) {
 		struct tegra_dma_channel *tdc = &tdma->channels[i];
@@ -1546,6 +1561,8 @@ static int tegra_dma_probe(struct platform_device *pdev)
 
 err_pm_disable:
 	pm_runtime_disable(&pdev->dev);
+
+err_clk_unprepare:
 	clk_unprepare(tdma->dma_clk);
 
 	return ret;
@@ -1565,26 +1582,6 @@ static int tegra_dma_remove(struct platform_device *pdev)
 static int tegra_dma_runtime_suspend(struct device *dev)
 {
 	struct tegra_dma *tdma = dev_get_drvdata(dev);
-	unsigned int i;
-
-	tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);
-	for (i = 0; i < tdma->chip_data->nr_channels; i++) {
-		struct tegra_dma_channel *tdc = &tdma->channels[i];
-		struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
-
-		/* Only save the state of DMA channels that are in use */
-		if (!tdc->config_init)
-			continue;
-
-		ch_reg->csr = tdc_read(tdc, TEGRA_APBDMA_CHAN_CSR);
-		ch_reg->ahb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBPTR);
-		ch_reg->apb_ptr = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBPTR);
-		ch_reg->ahb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_AHBSEQ);
-		ch_reg->apb_seq = tdc_read(tdc, TEGRA_APBDMA_CHAN_APBSEQ);
-		if (tdma->chip_data->support_separate_wcount_reg)
-			ch_reg->wcount = tdc_read(tdc,
-						  TEGRA_APBDMA_CHAN_WCOUNT);
-	}
 
 	clk_disable(tdma->dma_clk);
 
@@ -1594,46 +1591,51 @@ static int tegra_dma_runtime_suspend(struct device *dev)
 static int tegra_dma_runtime_resume(struct device *dev)
 {
 	struct tegra_dma *tdma = dev_get_drvdata(dev);
-	unsigned int i;
-	int ret;
 
-	ret = clk_enable(tdma->dma_clk);
-	if (ret < 0) {
-		dev_err(dev, "clk_enable failed: %d\n", ret);
-		return ret;
-	}
+	return clk_enable(tdma->dma_clk);
+}
 
-	tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);
-	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);
-	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);
+static int __maybe_unused tegra_dma_dev_suspend(struct device *dev)
+{
+	struct tegra_dma *tdma = dev_get_drvdata(dev);
+	unsigned long flags;
+	unsigned int i;
+	bool busy;
 
 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {
 		struct tegra_dma_channel *tdc = &tdma->channels[i];
-		struct tegra_dma_channel_regs *ch_reg = &tdc->channel_reg;
-
-		/* Only restore the state of DMA channels that are in use */
-		if (!tdc->config_init)
-			continue;
-
-		if (tdma->chip_data->support_separate_wcount_reg)
-			tdc_write(tdc, TEGRA_APBDMA_CHAN_WCOUNT,
-				  ch_reg->wcount);
-		tdc_write(tdc, TEGRA_APBDMA_CHAN_APBSEQ, ch_reg->apb_seq);
-		tdc_write(tdc, TEGRA_APBDMA_CHAN_APBPTR, ch_reg->apb_ptr);
-		tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBSEQ, ch_reg->ahb_seq);
-		tdc_write(tdc, TEGRA_APBDMA_CHAN_AHBPTR, ch_reg->ahb_ptr);
-		tdc_write(tdc, TEGRA_APBDMA_CHAN_CSR,
-			  ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB);
+
+		tasklet_kill(&tdc->tasklet);
+
+		spin_lock_irqsave(&tdc->lock, flags);
+		busy = tdc->busy;
+		spin_unlock_irqrestore(&tdc->lock, flags);
+
+		if (busy) {
+			dev_err(tdma->dev, "channel %u busy\n", i);
+			return -EBUSY;
+		}
 	}
 
-	return 0;
+	return pm_runtime_force_suspend(dev);
+}
+
+static int __maybe_unused tegra_dma_dev_resume(struct device *dev)
+{
+	struct tegra_dma *tdma = dev_get_drvdata(dev);
+	int err;
+
+	err = tegra_dma_init_hw(tdma);
+	if (err)
+		return err;
+
+	return pm_runtime_force_resume(dev);
 }
 
 static const struct dev_pm_ops tegra_dma_dev_pm_ops = {
 	SET_RUNTIME_PM_OPS(tegra_dma_runtime_suspend, tegra_dma_runtime_resume,
 			   NULL)
-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
-				pm_runtime_force_resume)
+	SET_SYSTEM_SLEEP_PM_OPS(tegra_dma_dev_suspend, tegra_dma_dev_resume)
 };
 
 static const struct of_device_id tegra_dma_of_match[] = {
-- 
2.24.0


  parent reply index

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-02 22:28 [PATCH v7 00/19] NVIDIA Tegra APB DMA driver fixes and improvements Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 01/19] dmaengine: tegra-apb: Fix use-after-free Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 02/19] dmaengine: tegra-apb: Prevent race conditions of tasklet vs free list Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 03/19] dmaengine: tegra-apb: Implement synchronization hook Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 04/19] dmaengine: tegra-apb: Prevent race conditions on channel's freeing Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 05/19] dmaengine: tegra-apb: Clean up tasklet releasing Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 06/19] dmaengine: tegra-apb: Use devm_platform_ioremap_resource Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 07/19] dmaengine: tegra-apb: Use devm_request_irq Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 08/19] dmaengine: tegra-apb: Fix coding style problems Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 09/19] dmaengine: tegra-apb: Remove unneeded initialization of tdc->config_init Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 10/19] dmaengine: tegra-apb: Remove assumptions about unavailable runtime PM Dmitry Osipenko
2020-02-04 14:51   ` Jon Hunter
2020-02-02 22:28 ` [PATCH v7 11/19] dmaengine: tegra-apb: Remove pending_sg_req checking from tdc_start_head_req Dmitry Osipenko
2020-02-04 14:53   ` Jon Hunter
2020-02-02 22:28 ` [PATCH v7 12/19] dmaengine: tegra-apb: Remove handling of unrealistic error condition Dmitry Osipenko
2020-02-04 11:52   ` Jon Hunter
2020-02-04 22:17     ` Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 13/19] dmaengine: tegra-apb: Don't stop cyclic DMA in a case of " Dmitry Osipenko
2020-02-04 12:02   ` Jon Hunter
2020-02-04 15:55     ` Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 14/19] dmaengine: tegra-apb: Keep clock enabled only during of DMA transfer Dmitry Osipenko
2020-02-06 13:50   ` Jon Hunter
2020-02-06 14:31     ` Dmitry Osipenko
2020-02-06 14:33       ` Jon Hunter
2020-02-02 22:28 ` Dmitry Osipenko [this message]
2020-02-02 22:28 ` [PATCH v7 16/19] dmaengine: tegra-apb: Add missing of_dma_controller_free Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 17/19] dmaengine: tegra-apb: Allow to compile as a loadable kernel module Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 18/19] dmaengine: tegra-apb: Remove MODULE_ALIAS Dmitry Osipenko
2020-02-02 22:28 ` [PATCH v7 19/19] dmaengine: tegra-apb: Support COMPILE_TEST Dmitry Osipenko

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