From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3715EC433DF for ; Thu, 28 May 2020 15:40:37 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1EA1E20814 for ; Thu, 28 May 2020 15:40:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404509AbgE1Pka (ORCPT ); Thu, 28 May 2020 11:40:30 -0400 Received: from mail.baikalelectronics.com ([87.245.175.226]:43184 "EHLO mail.baikalelectronics.ru" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404383AbgE1Pk1 (ORCPT ); Thu, 28 May 2020 11:40:27 -0400 Received: from localhost (unknown [127.0.0.1]) by mail.baikalelectronics.ru (Postfix) with ESMTP id B52C880307C0; Thu, 28 May 2020 15:40:23 +0000 (UTC) X-Virus-Scanned: amavisd-new at baikalelectronics.ru Received: from mail.baikalelectronics.ru ([127.0.0.1]) by localhost (mail.baikalelectronics.ru [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id YJY955QVHiku; Thu, 28 May 2020 18:40:23 +0300 (MSK) Date: Thu, 28 May 2020 18:40:22 +0300 From: Serge Semin To: Andy Shevchenko CC: Serge Semin , Vinod Koul , Viresh Kumar , Dan Williams , Alexey Malahov , Thomas Bogendoerfer , Arnd Bergmann , Rob Herring , , , , Subject: Re: [PATCH v3 09/10] dmaengine: dw: Introduce max burst length hw config Message-ID: <20200528154022.3reghhjcd4dnsr3g@mobilestation> References: <20200526225022.20405-1-Sergey.Semin@baikalelectronics.ru> <20200526225022.20405-10-Sergey.Semin@baikalelectronics.ru> <20200528145224.GT1634618@smile.fi.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20200528145224.GT1634618@smile.fi.intel.com> X-ClientProxiedBy: MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25) Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Thu, May 28, 2020 at 05:52:24PM +0300, Andy Shevchenko wrote: > On Wed, May 27, 2020 at 01:50:20AM +0300, Serge Semin wrote: > > IP core of the DW DMA controller may be synthesized with different > > max burst length of the transfers per each channel. According to Synopsis > > having the fixed maximum burst transactions length may provide some > > performance gain. At the same time setting up the source and destination > > multi size exceeding the max burst length limitation may cause a serious > > problems. In our case the DMA transaction just hangs up. In order to fix > > this lets introduce the max burst length platform config of the DW DMA > > controller device and don't let the DMA channels configuration code > > exceed the burst length hardware limitation. > > > > Note the maximum burst length parameter can be detected either in runtime > > from the DWC parameter registers or from the dedicated DT property. > > Depending on the IP core configuration the maximum value can vary from > > channel to channel so by overriding the channel slave max_burst capability > > we make sure a DMA consumer will get the channel-specific max burst > > length. > > ... > > > static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) > > { > > + struct dw_dma_chan *dwc = to_dw_dma_chan(chan); > > > > Perhaps, > > /* DesignWare DMA supports burst value from 0 */ > caps->min_burst = 0; Regarding min_burst being zero. I don't fully understand what it means. It means no burst or burst with minimum length or what? In fact DW DMA burst length starts from 1. Remember the burst-length run-time parameter we were arguing about? Anyway the driver makes sure that both 0 and 1 requested burst length are setup as burst length of 1 in the CTLx.SRC_MSIZE, CTLx.DST_MSIZE fields. I agree with the rest of your comments below. -Sergey > > > + caps->max_burst = dwc->max_burst; > > } > > ... > > > + *maxburst = clamp(*maxburst, 0U, dwc->max_burst); > > Shouldn't we do the same for iDMA 32-bit? Thus, perhaps do it in the core.c? > > > *maxburst = *maxburst > 1 ? fls(*maxburst) - 2 : 0; > > > + if (!of_property_read_u32_array(np, "snps,max-burst-len", mb, > > + nr_channels)) { > > + for (tmp = 0; tmp < nr_channels; tmp++) > > + pdata->max_burst[tmp] = mb[tmp]; > > I think we may read directly to the array. This ugly loops were introduced due > to type mismatch. (See below) > > > + } else { > > + for (tmp = 0; tmp < nr_channels; tmp++) > > + pdata->max_burst[tmp] = DW_DMA_MAX_BURST; > > + } > > And this will be effectively memset32(). > > > unsigned char nr_masters; > > unsigned char data_width[DW_DMA_MAX_NR_MASTERS]; > > unsigned char multi_block[DW_DMA_MAX_NR_CHANNELS]; > > + unsigned int max_burst[DW_DMA_MAX_NR_CHANNELS]; > > I think we have to stop with this kind of types and use directly what is in the > properties, i.e. > > u32 max_burst[...]; > > -- > With Best Regards, > Andy Shevchenko > >