From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 025A7C433DF for ; Fri, 29 May 2020 10:28:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id DB6702074B for ; Fri, 29 May 2020 10:28:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726161AbgE2K2A (ORCPT ); Fri, 29 May 2020 06:28:00 -0400 Received: from mga12.intel.com ([192.55.52.136]:15738 "EHLO mga12.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725920AbgE2K17 (ORCPT ); Fri, 29 May 2020 06:27:59 -0400 IronPort-SDR: Th5axlvECwaus3KrcUvre21AaF+RuirgxClLXOJr9ujYDRmFNUK+JIKehilj54ZNuWs+y9R7cP IO2UAbYW2D4A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2020 03:27:58 -0700 IronPort-SDR: yZWHEw6N3fJYIYszgq50Qzdz+p+4/7Wkrc+snophAHAc6hs9QifNQ+SJ6whwaHMfnngErhuYUu vrdcVzxbUVrw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,448,1583222400"; d="scan'208";a="469462825" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by fmsmga006.fm.intel.com with ESMTP; 29 May 2020 03:27:55 -0700 Received: from andy by smile with local (Exim 4.93) (envelope-from ) id 1jecF4-009ars-OL; Fri, 29 May 2020 13:27:58 +0300 Date: Fri, 29 May 2020 13:27:58 +0300 From: Andy Shevchenko To: Serge Semin Cc: Vinod Koul , Viresh Kumar , Dan Williams , Serge Semin , Alexey Malahov , Thomas Bogendoerfer , Arnd Bergmann , Rob Herring , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 11/11] dmaengine: dw: Initialize max_sg_nents capability Message-ID: <20200529102758.GF1634618@smile.fi.intel.com> References: <20200528222401.26941-1-Sergey.Semin@baikalelectronics.ru> <20200528222401.26941-12-Sergey.Semin@baikalelectronics.ru> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200528222401.26941-12-Sergey.Semin@baikalelectronics.ru> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org On Fri, May 29, 2020 at 01:24:01AM +0300, Serge Semin wrote: > Multi-block support provides a way to map the kernel-specific SG-table so > the DW DMA device would handle it as a whole instead of handling the > SG-list items or so called LLP block items one by one. So if true LLP > list isn't supported by the DW DMA engine, then soft-LLP mode will be > utilized to load and execute each LLP-block one by one. The soft-LLP mode > of the DMA transactions execution might not work well for some DMA > consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's > initialize the max_sg_nents DMA channels capability based on the nollp > flag state. If it's true, no hardware accelerated LLP is available and > max_sg_nents should be set with 1, which means that the DMA engine > can handle only a single SG list entry at a time. If noLLP is set to > false, then hardware accelerated LLP is supported and the DMA engine > can handle infinite number of SG entries in a single DMA transaction. Reviewed-by: Andy Shevchenko > > Signed-off-by: Serge Semin > Cc: Alexey Malahov > Cc: Thomas Bogendoerfer > Cc: Arnd Bergmann > Cc: Rob Herring > Cc: linux-mips@vger.kernel.org > Cc: devicetree@vger.kernel.org > > --- > > Changelog v3: > - This is a new patch created as a result of the discussion with Vinud and > Andy in the framework of DW DMA burst and LLP capabilities. > > Changelog v4: > - Use explicit if-else statement when assigning the max_sg_nents field. > --- > drivers/dma/dw/core.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index 60ef779fc5e0..b76eee75fde8 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps) > struct dw_dma_chan *dwc = to_dw_dma_chan(chan); > > caps->max_burst = dwc->max_burst; > + > + /* > + * It might be crucial for some devices to have the hardware > + * accelerated multi-block transfers supported, aka LLPs in DW DMAC > + * notation. So if LLPs are supported then max_sg_nents is set to > + * zero which means unlimited number of SG entries can be handled in a > + * single DMA transaction, otherwise it's just one SG entry. > + */ > + if (dwc->nollp) > + caps->max_sg_nents = 1; > + else > + caps->max_sg_nents = 0; > } > > int do_dma_probe(struct dw_dma_chip *chip) > -- > 2.26.2 > -- With Best Regards, Andy Shevchenko