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From: Serge Semin <>
To: Vinod Koul <>, Viresh Kumar <>,
	Andy Shevchenko <>,
	Dan Williams <>
Cc: Serge Semin <>,
	Serge Semin <>,
	Alexey Malahov <>,
	Pavel Parkhomenko <>,
	Peter Ujfalusi <>,
	Andy Shevchenko <>,
	Rob Herring <>, <>,
	<>, <>
Subject: [PATCH v8 10/10] dmaengine: dw: Initialize max_sg_burst capability
Date: Thu, 23 Jul 2020 03:58:48 +0300
Message-ID: <> (raw)
In-Reply-To: <>

Multi-block support provides a way to map the kernel-specific SG-table so
the DW DMA device would handle it as a whole instead of handling the
SG-list items or so called LLP block items one by one. So if true LLP
list isn't supported by the DW DMA engine, then soft-LLP mode will be
utilized to load and execute each LLP-block one by one. The soft-LLP mode
of the DMA transactions execution might not work well for some DMA
consumers like SPI due to its Tx and Rx buffers inter-dependency. Let's
initialize the max_sg_burst DMA channels capability based on the nollp
flag state. If it's true, no hardware accelerated LLP is available and
max_sg_burst should be set with 1, which means that the DMA engine
can handle only a single SG list entry at a time. If noLLP is set to
false, then hardware accelerated LLP is supported and the DMA engine
can handle infinite number of SG entries in a single DMA transaction.

Signed-off-by: Serge Semin <>
Reviewed-by: Andy Shevchenko <>


Changelog v3:
- This is a new patch created as a result of the discussion with Vinud and
  Andy in the framework of DW DMA burst and LLP capabilities.

Changelog v4:
- Use explicit if-else statement when assigning the max_sg_burst field.

Changelog v8:
- Replace max_sg_nents with max_sg_burst.
 drivers/dma/dw/core.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 588b9bae827c..eb9175133034 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1059,6 +1059,18 @@ static void dwc_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
 	struct dw_dma_chan *dwc = to_dw_dma_chan(chan);
 	caps->max_burst = dwc->max_burst;
+	/*
+	 * It might be crucial for some devices to have the hardware
+	 * accelerated multi-block transfers supported, aka LLPs in DW DMAC
+	 * notation. So if LLPs are supported then max_sg_burst is set to
+	 * zero which means unlimited number of SG entries can be handled in a
+	 * single DMA transaction, otherwise it's just one SG entry.
+	 */
+	if (dwc->nollp)
+		caps->max_sg_burst = 1;
+	else
+		caps->max_sg_burst = 0;
 int do_dma_probe(struct dw_dma_chip *chip)

  parent reply index

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-23  0:58 [PATCH v8 00/10] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account Serge Semin
2020-07-23  0:58 ` [PATCH v8 01/10] dt-bindings: dma: dw: Convert DW DMAC to DT binding Serge Semin
2020-07-23  0:58 ` [PATCH v8 02/10] dt-bindings: dma: dw: Add max burst transaction length property Serge Semin
2020-07-23  0:58 ` [PATCH v8 03/10] dmaengine: Introduce min burst length capability Serge Semin
2020-07-23  0:58 ` [PATCH v8 04/10] dmaengine: Introduce max SG burst capability Serge Semin
2020-07-23  0:58 ` [PATCH v8 05/10] dmaengine: Introduce DMA-device device_caps callback Serge Semin
2020-07-23  0:58 ` [PATCH v8 06/10] dmaengine: dw: Take HC_LLP flag into account for noLLP auto-config Serge Semin
2020-07-23  0:58 ` [PATCH v8 07/10] dmaengine: dw: Set DMA device max segment size parameter Serge Semin
2020-07-23  0:58 ` [PATCH v8 08/10] dmaengine: dw: Initialize min and max burst DMA device capability Serge Semin
2020-07-23  0:58 ` [PATCH v8 09/10] dmaengine: dw: Introduce max burst length hw config Serge Semin
2020-07-23  0:58 ` Serge Semin [this message]
2020-07-27  9:01 ` [PATCH v8 00/10] dmaengine: dw: Take Baikal-T1 SoC DW DMAC peculiarities into account Vinod Koul
2020-07-27 20:55   ` Serge Semin

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