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* [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware
@ 2020-07-17 12:09 Peter Ujfalusi
  2020-07-17 12:09 ` [PATCH 1/2] dmaengine: ti: k3-udma: Use defines for capabilities register parsing Peter Ujfalusi
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Peter Ujfalusi @ 2020-07-17 12:09 UTC (permalink / raw)
  To: vkoul; +Cc: dmaengine, dan.j.williams

Hi,

Newer versions of UDMAP have information on the number of different throughput
channels in it's CAP registers.

The driver can auto configure based on the information from the hardware isntead
a table within the match_data.

With this change we can use the same compatible string for identical versions of
UDMAP when only the number of UHCHAN and HCHAN is different.

Regards,
Peter
---
Peter Ujfalusi (2):
  dmaengine: ti: k3-udma: Use defines for capabilities register parsing
  dmaengine: ti: k3-udma: Query throughput level information from
    hardware

 drivers/dma/ti/k3-udma.c | 69 ++++++++++++++++++++--------------------
 drivers/dma/ti/k3-udma.h |  8 +++++
 2 files changed, 42 insertions(+), 35 deletions(-)

-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 1/2] dmaengine: ti: k3-udma: Use defines for capabilities register parsing
  2020-07-17 12:09 [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware Peter Ujfalusi
@ 2020-07-17 12:09 ` Peter Ujfalusi
  2020-07-17 12:09 ` [PATCH 2/2] dmaengine: ti: k3-udma: Query throughput level information from hardware Peter Ujfalusi
  2020-07-27  8:53 ` [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels " Vinod Koul
  2 siblings, 0 replies; 4+ messages in thread
From: Peter Ujfalusi @ 2020-07-17 12:09 UTC (permalink / raw)
  To: vkoul; +Cc: dmaengine, dan.j.williams

Add defines for the CAP register fields to make the code self explaining.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 drivers/dma/ti/k3-udma.c | 12 ++++++------
 drivers/dma/ti/k3-udma.h |  6 ++++++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 336fb6472cac..0ac6c440f536 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -3207,13 +3207,13 @@ static int udma_setup_resources(struct udma_dev *ud)
 						    "ti,sci-rm-range-rchan",
 						    "ti,sci-rm-range-rflow" };
 
-	cap2 = udma_read(ud->mmrs[MMR_GCFG], 0x28);
-	cap3 = udma_read(ud->mmrs[MMR_GCFG], 0x2c);
+	cap2 = udma_read(ud->mmrs[MMR_GCFG], UDMA_CAP_REG(2));
+	cap3 = udma_read(ud->mmrs[MMR_GCFG], UDMA_CAP_REG(3));
 
-	ud->rflow_cnt = cap3 & 0x3fff;
-	ud->tchan_cnt = cap2 & 0x1ff;
-	ud->echan_cnt = (cap2 >> 9) & 0x1ff;
-	ud->rchan_cnt = (cap2 >> 18) & 0x1ff;
+	ud->rflow_cnt = UDMA_CAP3_RFLOW_CNT(cap3);
+	ud->tchan_cnt = UDMA_CAP2_TCHAN_CNT(cap2);
+	ud->echan_cnt = UDMA_CAP2_ECHAN_CNT(cap2);
+	ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2);
 	ch_count  = ud->tchan_cnt + ud->rchan_cnt;
 
 	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index a8ea1138e1a5..9534f0ca29f4 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -37,6 +37,12 @@
 #define UDMA_CHAN_RT_BCNT_REG		0x408
 #define UDMA_CHAN_RT_SBCNT_REG		0x410
 
+/* UDMA_CAP Registers */
+#define UDMA_CAP2_TCHAN_CNT(val)	((val) & 0x1ff)
+#define UDMA_CAP2_ECHAN_CNT(val)	(((val) >> 9) & 0x1ff)
+#define UDMA_CAP2_RCHAN_CNT(val)	(((val) >> 18) & 0x1ff)
+#define UDMA_CAP3_RFLOW_CNT(val)	((val) & 0x3fff)
+
 /* UDMA_CHAN_RT_CTL_REG */
 #define UDMA_CHAN_RT_CTL_EN		BIT(31)
 #define UDMA_CHAN_RT_CTL_TDOWN		BIT(30)
-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [PATCH 2/2] dmaengine: ti: k3-udma: Query throughput level information from hardware
  2020-07-17 12:09 [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware Peter Ujfalusi
  2020-07-17 12:09 ` [PATCH 1/2] dmaengine: ti: k3-udma: Use defines for capabilities register parsing Peter Ujfalusi
@ 2020-07-17 12:09 ` Peter Ujfalusi
  2020-07-27  8:53 ` [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels " Vinod Koul
  2 siblings, 0 replies; 4+ messages in thread
From: Peter Ujfalusi @ 2020-07-17 12:09 UTC (permalink / raw)
  To: vkoul; +Cc: dmaengine, dan.j.williams

The CAP3 register contains information about the number of
HCHAN (High Capacity) and UCHAN (Ultra High Capacity) channels in UDMAP.

Based on this information the start indexes of the levels can be calculated
without a need of a table in the match data.

On am654 the CAP3 does not contain information about the number different
channels. Set up the tpl information based on the available documentation.

This change will allow to use the same compatible for different SoCs where
the only difference is the number of channel types.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 drivers/dma/ti/k3-udma.c | 57 ++++++++++++++++++++--------------------
 drivers/dma/ti/k3-udma.h |  2 ++
 2 files changed, 30 insertions(+), 29 deletions(-)

diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index 0ac6c440f536..d159c793d625 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -92,9 +92,6 @@ struct udma_match_data {
 	u32 flags;
 	u32 statictr_z_mask;
 	u32 rchan_oes_offset;
-
-	u8 tpl_levels;
-	u32 level_start_idx[];
 };
 
 struct udma_hwdesc {
@@ -121,6 +118,9 @@ struct udma_dev {
 	void __iomem *mmrs[MMR_LAST];
 	const struct udma_match_data *match_data;
 
+	u8 tpl_levels;
+	u32 tpl_start_idx[3];
+
 	size_t desc_align; /* alignment to use for descriptors */
 
 	struct udma_tisci_rm tisci_rm;
@@ -1210,10 +1210,10 @@ static struct udma_##res *__udma_reserve_##res(struct udma_dev *ud,	\
 	} else {							\
 		int start;						\
 									\
-		if (tpl >= ud->match_data->tpl_levels)			\
-			tpl = ud->match_data->tpl_levels - 1;		\
+		if (tpl >= ud->tpl_levels)				\
+			tpl = ud->tpl_levels - 1;			\
 									\
-		start = ud->match_data->level_start_idx[tpl];		\
+		start = ud->tpl_start_idx[tpl];				\
 									\
 		id = find_next_zero_bit(ud->res##_map, ud->res##_cnt,	\
 					start);				\
@@ -1262,7 +1262,6 @@ static int udma_get_rchan(struct udma_chan *uc)
 static int udma_get_chan_pair(struct udma_chan *uc)
 {
 	struct udma_dev *ud = uc->ud;
-	const struct udma_match_data *match_data = ud->match_data;
 	int chan_id, end;
 
 	if ((uc->tchan && uc->rchan) && uc->tchan->id == uc->rchan->id) {
@@ -1284,7 +1283,7 @@ static int udma_get_chan_pair(struct udma_chan *uc)
 	/* Can be optimized, but let's have it like this for now */
 	end = min(ud->tchan_cnt, ud->rchan_cnt);
 	/* Try to use the highest TPL channel pair for MEM_TO_MEM channels */
-	chan_id = match_data->level_start_idx[match_data->tpl_levels - 1];
+	chan_id = ud->tpl_start_idx[ud->tpl_levels - 1];
 	for (; chan_id < end; chan_id++) {
 		if (!test_bit(chan_id, ud->tchan_map) &&
 		    !test_bit(chan_id, ud->rchan_map))
@@ -3115,11 +3114,6 @@ static struct udma_match_data am654_main_data = {
 	.enable_memcpy_support = true,
 	.statictr_z_mask = GENMASK(11, 0),
 	.rchan_oes_offset = 0x2000,
-	.tpl_levels = 2,
-	.level_start_idx = {
-		[0] = 8, /* Normal channels */
-		[1] = 0, /* High Throughput channels */
-	},
 };
 
 static struct udma_match_data am654_mcu_data = {
@@ -3127,11 +3121,6 @@ static struct udma_match_data am654_mcu_data = {
 	.enable_memcpy_support = false,
 	.statictr_z_mask = GENMASK(11, 0),
 	.rchan_oes_offset = 0x2000,
-	.tpl_levels = 2,
-	.level_start_idx = {
-		[0] = 2, /* Normal channels */
-		[1] = 0, /* High Throughput channels */
-	},
 };
 
 static struct udma_match_data j721e_main_data = {
@@ -3140,12 +3129,6 @@ static struct udma_match_data j721e_main_data = {
 	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST,
 	.statictr_z_mask = GENMASK(23, 0),
 	.rchan_oes_offset = 0x400,
-	.tpl_levels = 3,
-	.level_start_idx = {
-		[0] = 16, /* Normal channels */
-		[1] = 4, /* High Throughput channels */
-		[2] = 0, /* Ultra High Throughput channels */
-	},
 };
 
 static struct udma_match_data j721e_mcu_data = {
@@ -3154,11 +3137,6 @@ static struct udma_match_data j721e_mcu_data = {
 	.flags = UDMA_FLAG_PDMA_ACC32 | UDMA_FLAG_PDMA_BURST,
 	.statictr_z_mask = GENMASK(23, 0),
 	.rchan_oes_offset = 0x400,
-	.tpl_levels = 2,
-	.level_start_idx = {
-		[0] = 2, /* Normal channels */
-		[1] = 0, /* High Throughput channels */
-	},
 };
 
 static const struct of_device_id udma_of_match[] = {
@@ -3216,6 +3194,27 @@ static int udma_setup_resources(struct udma_dev *ud)
 	ud->rchan_cnt = UDMA_CAP2_RCHAN_CNT(cap2);
 	ch_count  = ud->tchan_cnt + ud->rchan_cnt;
 
+	/* Set up the throughput level start indexes */
+	if (of_device_is_compatible(dev->of_node,
+				    "ti,am654-navss-main-udmap")) {
+		ud->tpl_levels = 2;
+		ud->tpl_start_idx[0] = 8;
+	} else if (of_device_is_compatible(dev->of_node,
+					   "ti,am654-navss-mcu-udmap")) {
+		ud->tpl_levels = 2;
+		ud->tpl_start_idx[0] = 2;
+	} else if (UDMA_CAP3_UCHAN_CNT(cap3)) {
+		ud->tpl_levels = 3;
+		ud->tpl_start_idx[1] = UDMA_CAP3_UCHAN_CNT(cap3);
+		ud->tpl_start_idx[0] = ud->tpl_start_idx[1] +
+				       UDMA_CAP3_HCHAN_CNT(cap3);
+	} else if (UDMA_CAP3_HCHAN_CNT(cap3)) {
+		ud->tpl_levels = 2;
+		ud->tpl_start_idx[0] = UDMA_CAP3_HCHAN_CNT(cap3);
+	} else {
+		ud->tpl_levels = 1;
+	}
+
 	ud->tchan_map = devm_kmalloc_array(dev, BITS_TO_LONGS(ud->tchan_cnt),
 					   sizeof(unsigned long), GFP_KERNEL);
 	ud->tchans = devm_kcalloc(dev, ud->tchan_cnt, sizeof(*ud->tchans),
diff --git a/drivers/dma/ti/k3-udma.h b/drivers/dma/ti/k3-udma.h
index 9534f0ca29f4..09c4529e013d 100644
--- a/drivers/dma/ti/k3-udma.h
+++ b/drivers/dma/ti/k3-udma.h
@@ -42,6 +42,8 @@
 #define UDMA_CAP2_ECHAN_CNT(val)	(((val) >> 9) & 0x1ff)
 #define UDMA_CAP2_RCHAN_CNT(val)	(((val) >> 18) & 0x1ff)
 #define UDMA_CAP3_RFLOW_CNT(val)	((val) & 0x3fff)
+#define UDMA_CAP3_HCHAN_CNT(val)	(((val) >> 14) & 0x1ff)
+#define UDMA_CAP3_UCHAN_CNT(val)	(((val) >> 23) & 0x1ff)
 
 /* UDMA_CHAN_RT_CTL_REG */
 #define UDMA_CHAN_RT_CTL_EN		BIT(31)
-- 
Peter

Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware
  2020-07-17 12:09 [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware Peter Ujfalusi
  2020-07-17 12:09 ` [PATCH 1/2] dmaengine: ti: k3-udma: Use defines for capabilities register parsing Peter Ujfalusi
  2020-07-17 12:09 ` [PATCH 2/2] dmaengine: ti: k3-udma: Query throughput level information from hardware Peter Ujfalusi
@ 2020-07-27  8:53 ` Vinod Koul
  2 siblings, 0 replies; 4+ messages in thread
From: Vinod Koul @ 2020-07-27  8:53 UTC (permalink / raw)
  To: Peter Ujfalusi; +Cc: dmaengine, dan.j.williams

On 17-07-20, 15:09, Peter Ujfalusi wrote:
> Hi,
> 
> Newer versions of UDMAP have information on the number of different throughput
> channels in it's CAP registers.
> 
> The driver can auto configure based on the information from the hardware isntead
> a table within the match_data.
> 
> With this change we can use the same compatible string for identical versions of
> UDMAP when only the number of UHCHAN and HCHAN is different.

Applied, thanks

-- 
~Vinod

^ permalink raw reply	[flat|nested] 4+ messages in thread

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-- links below jump to the message on this page --
2020-07-17 12:09 [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels from hardware Peter Ujfalusi
2020-07-17 12:09 ` [PATCH 1/2] dmaengine: ti: k3-udma: Use defines for capabilities register parsing Peter Ujfalusi
2020-07-17 12:09 ` [PATCH 2/2] dmaengine: ti: k3-udma: Query throughput level information from hardware Peter Ujfalusi
2020-07-27  8:53 ` [PATCH 0/2] dmaengine: ti: k3-udma: Get supported throughput levels " Vinod Koul

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