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From: Serge Semin <>
To: Vinod Koul <>, Viresh Kumar <>,
	Andy Shevchenko <>,
	Rob Herring <>
Cc: Serge Semin <>,
	Serge Semin <>,
	Alexey Malahov <>,
	Pavel Parkhomenko <>,
	Peter Ujfalusi <>,
	Andy Shevchenko <>,
	<>, <>,
Subject: [PATCH v2 1/5] dt-bindings: dma: dw: Add optional DMA-channels mask cell support
Date: Fri, 31 Jul 2020 23:08:22 +0300
Message-ID: <> (raw)
In-Reply-To: <>

Each DW DMA controller channel can be synthesized with different
parameters like maximum burst-length, multi-block support, maximum data
width, etc. Most of these parameters determine the DW DMAC channels
performance in its own aspect. On the other hand these parameters can
be implicitly responsible for the channels performance degradation
(for instance multi-block support is a very useful feature, but having
it disabled during the DW DMAC synthesize will provide a more optimized
core). Since DMA slave devices may have critical dependency on the DMA
engine performance, let's provide a way for the slave devices to have
the DMA-channels allocated from a pool of the channels, which according
to the system engineer fulfill their performance requirements.

The pool is determined by a mask optionally specified in the fifth
DMA-cell of the DMA DT-property. If the fifth cell is omitted from the
phandle arguments or the mask is zero, then the allocation will be
performed from a set of all channels provided by the DMA controller.

Signed-off-by: Serge Semin <>
 .../devicetree/bindings/dma/snps,dma-spear1340.yaml        | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
index 20870f5c14dd..ef1d6879c158 100644
--- a/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dma-spear1340.yaml
@@ -18,12 +18,15 @@ properties:
     const: snps,dma-spear1340
-    const: 3
+    minimum: 3
+    maximum: 4
     description: |
       First cell is a phandle pointing to the DMA controller. Second one is
       the DMA request line number. Third cell is the memory master identifier
       for transfers on dynamically allocated channel. Fourth cell is the
-      peripheral master identifier for transfers on an allocated channel.
+      peripheral master identifier for transfers on an allocated channel. Fifth
+      cell is an optional mask of the DMA channels permitted to be allocated
+      for the corresponding client device.
     maxItems: 1

  reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-31 20:08 [PATCH v2 0/5] dmaengine: dw: Introduce non-mem peripherals optimizations Serge Semin
2020-07-31 20:08 ` Serge Semin [this message]
2020-08-03 21:51   ` [PATCH v2 1/5] dt-bindings: dma: dw: Add optional DMA-channels mask cell support Rob Herring
2020-07-31 20:08 ` [PATCH v2 2/5] dmaengine: dw: Activate FIFO-mode for memory peripherals only Serge Semin
2020-07-31 20:08 ` [PATCH v2 3/5] dmaengine: dw: Discard dlen from the dev-to-mem xfer width calculation Serge Semin
2020-07-31 20:08 ` [PATCH v2 4/5] dmaengine: dw: Ignore burst setting for memory peripherals Serge Semin
2020-07-31 20:08 ` [PATCH v2 5/5] dmaengine: dw: Add DMA-channels mask cell support Serge Semin

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