From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6681BC43467 for ; Thu, 8 Oct 2020 12:32:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1CA85217BA for ; Thu, 8 Oct 2020 12:32:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602160337; bh=+Jls9iCpTRcSMWAYCqPr4gisGOnMftsEieh9dAsauXU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=VlFwEtR88fNv/dU3YWqQYEExKyjKBn4r/y69uOKT1o8sJWFDfmyYoqmW2YLO9wLso mnvFoWmeYs2Rt9Ln3hRj8OXiMTPh8a2dtfW90SOYAXS5axCx82e0K8ZbK1McqfOXdX hTIkWJLuj1FxOYioVyrkX+4662Sch1z1LP4XZgp4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729918AbgJHMcN (ORCPT ); Thu, 8 Oct 2020 08:32:13 -0400 Received: from mail.kernel.org ([198.145.29.99]:57898 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725802AbgJHMcM (ORCPT ); Thu, 8 Oct 2020 08:32:12 -0400 Received: from localhost.localdomain (unknown [122.182.224.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E1B8E2184D; Thu, 8 Oct 2020 12:32:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1602160331; bh=+Jls9iCpTRcSMWAYCqPr4gisGOnMftsEieh9dAsauXU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KHUXb6RY/yegeogZ0ayUAnShIfwhfvgUNiAzFmDHg4aqhT+6FY4GwcQnghYMd7PlP 2LDIaQnFKCOLsDvvv2l4vBjBGI7MF2cN//+ZMGth+fkNhzN2gkyx/8Z/Kv1hEFo/fD P1XBy4KCk/CeZDGEvhh44bLMzBCMOVJKrem4rKV8= From: Vinod Koul To: dmaengine@vger.kernel.org Cc: Vinod Koul , Rob Herring , Bjorn Andersson , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Peter Ujfalusi Subject: [PATCH v4 1/3] dt-bindings: dmaengine: Document qcom,gpi dma binding Date: Thu, 8 Oct 2020 18:01:49 +0530 Message-Id: <20201008123151.764238-2-vkoul@kernel.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201008123151.764238-1-vkoul@kernel.org> References: <20201008123151.764238-1-vkoul@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs Signed-off-by: Vinod Koul --- .../devicetree/bindings/dma/qcom,gpi.yaml | 86 +++++++++++++++++++ include/dt-bindings/dma/qcom-gpi.h | 11 +++ 2 files changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/qcom,gpi.yaml create mode 100644 include/dt-bindings/dma/qcom-gpi.h diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml new file mode 100644 index 000000000000..4470c1b2fd6c --- /dev/null +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies Inc GPI DMA controller + +maintainers: + - Vinod Koul + +description: | + QCOM GPI DMA controller provides DMA capabilities for + peripheral buses such as I2C, UART, and SPI. + +allOf: + - $ref: "dma-controller.yaml#" + +properties: + compatible: + enum: + - qcom,sdm845-gpi-dma + + reg: + maxItems: 1 + + interrupts: + description: + Interrupt lines for each GPI instance + maxItems: 13 + + "#dma-cells": + const: 3 + description: > + DMA clients must use the format described in dma.txt, giving a phandle + to the DMA controller plus the following 3 integer cells: + - channel: if set to 0xffffffff, any available channel will be allocated + for the client. Otherwise, the exact channel specified will be used. + - seid: serial id of the client as defined in the SoC documentation. + - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h + + iommus: + maxItems: 1 + + dma-channels: + maximum: 31 + + dma-channel-mask: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + - iommus + - dma-channels + - dma-channel-mask + +examples: + - | + #include + #include + gpi_dma0: dma-controller@800000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <3>; + reg = <0x00800000 0x60000>; + iommus = <&apps_smmu 0x0016 0x0>; + dma-channels = <13>; + dma-channel-mask = <0xfa>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + +... diff --git a/include/dt-bindings/dma/qcom-gpi.h b/include/dt-bindings/dma/qcom-gpi.h new file mode 100644 index 000000000000..71f79eb7614c --- /dev/null +++ b/include/dt-bindings/dma/qcom-gpi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2020, Linaro Ltd. */ + +#ifndef __DT_BINDINGS_DMA_QCOM_GPI_H__ +#define __DT_BINDINGS_DMA_QCOM_GPI_H__ + +#define QCOM_GPI_SPI 1 +#define QCOM_GPI_UART 2 +#define QCOM_GPI_I2C 3 + +#endif /* __DT_BINDINGS_DMA_QCOM_GPI_H__ */ -- 2.26.2