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Date:   Fri, 9 Oct 2020 09:49:45 -0300
From:   Jason Gunthorpe <jgg@nvidia.com>
To:     "Raj, Ashok" <ashok.raj@intel.com>
CC:     Thomas Gleixner <tglx@linutronix.de>,
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Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm
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On Fri, Oct 09, 2020 at 05:43:07AM -0700, Raj, Ashok wrote:
> On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote:
> > On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
> > 
> > > Not randomly put there Jason :-).. There is a good reason for it. 
> > 
> > Sure the PASID value being associated with the IRQ make sense, but
> > combining that register with the interrupt mask is just a compltely
> > random thing to do.
> 
> Hummm... Not sure what you are complaining.. but in any case giving
> hardware a more efficient way to store interrupt entries breaking any
> boundaries that maybe implied by the spec is why IMS was defined.

I'm saying this PASID stuff is just some HW detail of IDXD and nothing
that the core irqchip code should concern itself with

Jason