From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
To: dmaengine@vger.kernel.org
Cc: Vinod Koul <vkoul@kernel.org>,
Michal Simek <michal.simek@xilinx.com>,
Jianqiang Chen <jianqian@xilinx.com>,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/4] dmaengine: xilinx: dpdma: Limit descriptor IDs to 16 bits
Date: Thu, 20 May 2021 18:24:20 +0300 [thread overview]
Message-ID: <20210520152420.23986-5-laurent.pinchart@ideasonboard.com> (raw)
In-Reply-To: <20210520152420.23986-1-laurent.pinchart@ideasonboard.com>
While the descriptor ID is stored in a 32-bit field in the hardware
descriptor, only 16 bits are used by the hardware and are reported
through the XILINX_DPDMA_CH_DESC_ID register. Failure to handle the
wrap-around results in a descriptor ID mismatch after 65536 frames. Fix
it.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
drivers/dma/xilinx/xilinx_dpdma.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dpdma.c b/drivers/dma/xilinx/xilinx_dpdma.c
index 5834f8614a58..6a8bb977fc7a 100644
--- a/drivers/dma/xilinx/xilinx_dpdma.c
+++ b/drivers/dma/xilinx/xilinx_dpdma.c
@@ -113,6 +113,7 @@
#define XILINX_DPDMA_CH_VDO 0x020
#define XILINX_DPDMA_CH_PYLD_SZ 0x024
#define XILINX_DPDMA_CH_DESC_ID 0x028
+#define XILINX_DPDMA_CH_DESC_ID_MASK GENMASK(15, 0)
/* DPDMA descriptor fields */
#define XILINX_DPDMA_DESC_CONTROL_PREEMBLE 0xa5
@@ -867,7 +868,8 @@ static void xilinx_dpdma_chan_queue_transfer(struct xilinx_dpdma_chan *chan)
* will be used, but it should be enough.
*/
list_for_each_entry(sw_desc, &desc->descriptors, node)
- sw_desc->hw.desc_id = desc->vdesc.tx.cookie;
+ sw_desc->hw.desc_id = desc->vdesc.tx.cookie
+ & XILINX_DPDMA_CH_DESC_ID_MASK;
sw_desc = list_first_entry(&desc->descriptors,
struct xilinx_dpdma_sw_desc, node);
@@ -1090,7 +1092,8 @@ static void xilinx_dpdma_chan_vsync_irq(struct xilinx_dpdma_chan *chan)
if (!chan->running || !pending)
goto out;
- desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID);
+ desc_id = dpdma_read(chan->reg, XILINX_DPDMA_CH_DESC_ID)
+ & XILINX_DPDMA_CH_DESC_ID_MASK;
/* If the retrigger raced with vsync, retry at the next frame. */
sw_desc = list_first_entry(&pending->descriptors,
--
Regards,
Laurent Pinchart
next prev parent reply other threads:[~2021-05-20 15:25 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-20 15:24 [PATCH 0/4] dmaengine: xilinx: dpdma: Fix freeze after 64k frames Laurent Pinchart
2021-05-20 15:24 ` [PATCH 1/4] dmaengine: xilinx: dpdma: Add missing dependencies to Kconfig Laurent Pinchart
2021-05-20 15:24 ` [PATCH 2/4] dmaengine: xilinx: dpdma: Print channel number in kernel log messages Laurent Pinchart
2021-05-20 15:24 ` [PATCH 3/4] dmaengine: xilinx: dpdma: Print debug message when losing vsync race Laurent Pinchart
2021-05-20 15:24 ` Laurent Pinchart [this message]
2021-05-27 16:35 ` [PATCH 0/4] dmaengine: xilinx: dpdma: Fix freeze after 64k frames Jianqiang Chen
2021-05-31 4:08 ` Vinod Koul
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