* [PATCH 0/5] Add RZ/G2L DMAC support
@ 2021-06-11 11:36 Biju Das
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
2021-06-11 11:36 ` [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
0 siblings, 2 replies; 19+ messages in thread
From: Biju Das @ 2021-06-11 11:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring
Cc: Biju Das, Chris Brandt, dmaengine, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
This patch series add basic support for RZ/G2L DMAC driver.
It is based on the work done by Chris Brandt for RZ/A DMA driver.
This patch set is based on master branch [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/
Biju Das (5):
dt-bindings: dma: Document RZ/G2L bindings
drivers: clk: renesas: r9a07g044-cpg: Add DMAC clocks
drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
arm64: dts: renesas: r9a07g044: Add DMAC support
arm64: defconfig: Enable DMA controller for RZ/G2L SoC's
.../bindings/dma/renesas,rz-dmac.yaml | 132 +++
arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 38 +
arch/arm64/configs/defconfig | 1 +
drivers/clk/renesas/r9a07g044-cpg.c | 3 +
drivers/dma/sh/Kconfig | 8 +
drivers/dma/sh/Makefile | 1 +
drivers/dma/sh/rz-dmac.c | 1050 +++++++++++++++++
7 files changed, 1233 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
create mode 100644 drivers/dma/sh/rz-dmac.c
--
2.17.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 11:36 [PATCH 0/5] Add RZ/G2L DMAC support Biju Das
@ 2021-06-11 11:36 ` Biju Das
2021-06-11 17:55 ` Rob Herring
` (2 more replies)
2021-06-11 11:36 ` [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
1 sibling, 3 replies; 19+ messages in thread
From: Biju Das @ 2021-06-11 11:36 UTC (permalink / raw)
To: Vinod Koul, Rob Herring
Cc: Biju Das, Chris Brandt, dmaengine, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
Document RZ/G2L DMAC bindings.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
.../bindings/dma/renesas,rz-dmac.yaml | 132 ++++++++++++++++++
1 file changed, 132 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
new file mode 100644
index 000000000000..df54bd6ddfd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/G2L DMA Controller
+
+maintainers:
+ - Biju Das <biju.das.jz@bp.renesas.com>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
+ - const: renesas,rz-dmac
+
+ reg:
+ items:
+ - description: Control and channel register block
+ - description: DMA extension resource selector block
+
+ interrupts:
+ maxItems: 17
+
+ interrupt-names:
+ maxItems: 17
+ items:
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - pattern: "^ch([0-9]|1[0-5])$"
+ - const: error
+
+ clocks:
+ maxItems: 1
+
+ '#dma-cells':
+ const: 1
+ description:
+ The cell specifies the MID/RID of the DMAC port connected to
+ the DMA client.
+
+ dma-channels:
+ const: 16
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ renesas,rz-dmac-slavecfg:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ DMA configuration for a slave channel. Each channel must have an array of
+ 3 items as below.
+ first item in the array is MID+RID
+ second item in the array is slave src or dst address
+ third item in the array is channel configuration value.
+ items:
+ minItems: 3
+ maxItems: 48
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+ - '#dma-cells'
+ - dma-channels
+ - power-domains
+ - resets
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/r9a07g044-cpg.h>
+
+ dmac: dma-controller@11820000 {
+ compatible = "renesas,dmac-r9a07g044",
+ "renesas,rz-dmac";
+ reg = <0x11820000 0x10000>,
+ <0x11830000 0x10000>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "error";
+ clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
+ power-domains = <&cpg>;
+ resets = <&cpg R9A07G044_CLK_DMAC>;
+ #dma-cells = <1>;
+ dma-channels = <16>;
+ renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
2021-06-11 11:36 [PATCH 0/5] Add RZ/G2L DMAC support Biju Das
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
@ 2021-06-11 11:36 ` Biju Das
2021-06-16 10:31 ` Vinod Koul
1 sibling, 1 reply; 19+ messages in thread
From: Biju Das @ 2021-06-11 11:36 UTC (permalink / raw)
To: Vinod Koul
Cc: Biju Das, Lad Prabhakar, Chris Paterson, Geert Uytterhoeven,
dmaengine, Chris Brandt, linux-renesas-soc
Add DMA Controller driver for RZ/G2L SoC.
Based on the work done by Chris Brandt for RZ/A DMA driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
drivers/dma/sh/Kconfig | 8 +
drivers/dma/sh/Makefile | 1 +
drivers/dma/sh/rz-dmac.c | 1050 ++++++++++++++++++++++++++++++++++++++
3 files changed, 1059 insertions(+)
create mode 100644 drivers/dma/sh/rz-dmac.c
diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
index 13437323a85b..280a6d359e36 100644
--- a/drivers/dma/sh/Kconfig
+++ b/drivers/dma/sh/Kconfig
@@ -47,3 +47,11 @@ config RENESAS_USB_DMAC
help
This driver supports the USB-DMA controller found in the Renesas
SoCs.
+
+config RZ_DMAC
+ tristate "Renesas RZ/G2L Controller"
+ depends on ARCH_R9A07G044 || COMPILE_TEST
+ select RENESAS_DMA
+ help
+ This driver supports the general purpose DMA controller found in the
+ Renesas RZ/G2L SoC variants.
diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
index 112fbd22bb3f..9b2927f543bf 100644
--- a/drivers/dma/sh/Makefile
+++ b/drivers/dma/sh/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
+obj-$(CONFIG_RZ_DMAC) += rz-dmac.o
diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
new file mode 100644
index 000000000000..87a902ba3cfa
--- /dev/null
+++ b/drivers/dma/sh/rz-dmac.c
@@ -0,0 +1,1050 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Renesas RZ/G2L Controller Driver
+ *
+ * Based on imx-dma.c
+ *
+ * Copyright (C) 2021 Renesas Electronics Corp.
+ * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
+ * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_dma.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include "../dmaengine.h"
+
+struct rz_dmac_slave_config {
+ u32 mid_rid;
+ dma_addr_t addr;
+ u32 chcfg;
+};
+
+enum rz_dmac_prep_type {
+ RZ_DMAC_DESC_MEMCPY,
+ RZ_DMAC_DESC_SLAVE_SG,
+};
+
+struct rz_lmdesc {
+ u32 header;
+ u32 sa;
+ u32 da;
+ u32 tb;
+ u32 chcfg;
+ u32 chitvl;
+ u32 chext;
+ u32 nxla;
+};
+
+struct rz_dmac_desc {
+ struct list_head node;
+ struct dma_async_tx_descriptor desc;
+ enum dma_status status;
+ dma_addr_t src;
+ dma_addr_t dest;
+ size_t len;
+ enum dma_transfer_direction direction;
+ enum rz_dmac_prep_type type;
+ /* For memcpy */
+ unsigned int config_port;
+ unsigned int config_mem;
+ /* For slave sg */
+ struct scatterlist *sg;
+ unsigned int sgcount;
+};
+
+struct rz_dmac_channel {
+ struct rz_dmac_engine *rzdma;
+ unsigned int index;
+ int irq;
+
+ spinlock_t lock;
+ struct list_head ld_free;
+ struct list_head ld_queue;
+ struct list_head ld_active;
+
+ int descs_allocated;
+ enum dma_slave_buswidth word_size;
+ dma_addr_t per_address;
+ struct dma_chan chan;
+ struct dma_async_tx_descriptor desc;
+ enum dma_status status;
+
+ const struct rz_dmac_slave_config *slave;
+ void __iomem *ch_base;
+ void __iomem *ch_cmn_base;
+
+ struct {
+ struct rz_lmdesc *base;
+ struct rz_lmdesc *head;
+ struct rz_lmdesc *tail;
+ int valid;
+ dma_addr_t base_dma;
+ } lmdesc;
+
+ u32 chcfg;
+ u32 chctrl;
+
+ struct {
+ int issue;
+ int prep_slave_sg;
+ } stat;
+};
+
+#define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_channel, chan)
+
+struct rz_dmac_engine {
+ struct dma_device dma_device;
+ struct device_dma_parameters dma_parms;
+ struct device *dev;
+ void __iomem *base;
+ void __iomem *ext_base;
+
+ spinlock_t lock;
+ struct rz_dmac_channel *channel;
+ unsigned int n_channels;
+ struct rz_dmac_slave_config *slave;
+ int slave_num;
+};
+
+/* -----------------------------------------------------------------------------
+ * Registers
+ */
+
+#define CHSTAT 0x0024
+#define CHCTRL 0x0028
+#define CHCFG 0x002c
+#define CHITVL 0x0030
+#define CHEXT 0x0034
+#define NXLA 0x0038
+#define CRLA 0x003c
+
+#define DCTRL 0x0000
+#define DSTAT_EN 0x0010
+#define DSTAT_ER 0x0014
+#define DSTAT_END 0x0018
+#define DSTAT_TC 0x001c
+#define DSTAT_SUS 0x0020
+
+#define EACH_CHANNEL_OFFSET 0x0040
+#define CHANNEL_0_7_OFFSET 0x0000
+#define CHANNEL_0_7_COMMON_BASE 0x0300
+#define CHANNEL_8_15_OFFSET 0x0400
+#define CHANNEL_8_15_COMMON_BASE 0x0700
+
+#define CHSTAT_TC BIT(6)
+#define CHSTAT_END BIT(5)
+#define CHSTAT_ER BIT(4)
+#define CHSTAT_EN BIT(0)
+
+#define CHCTRL_CLRINTMSK BIT(17)
+#define CHCTRL_SETINTMSK BIT(16)
+#define CHCTRL_CLRSUS BIT(9)
+#define CHCTRL_SETSUS BIT(8)
+#define CHCTRL_CLRTC BIT(6)
+#define CHCTRL_CLREND BIT(5)
+#define CHCTRL_CLRRQ BIT(4)
+#define CHCTRL_SWRST BIT(3)
+#define CHCTRL_STG BIT(2)
+#define CHCTRL_CLREN BIT(1)
+#define CHCTRL_SETEN BIT(0)
+#define CHCTRL_DEFAULT (CHCTRL_CLRINTMSK | CHCTRL_CLRSUS | \
+ CHCTRL_CLRTC | CHCTRL_CLREND | \
+ CHCTRL_CLRRQ | CHCTRL_SWRST | \
+ CHCTRL_CLREN)
+
+#define CHCFG_DMS BIT(31)
+#define CHCFG_DEM BIT(24)
+#define CHCFG_DAD BIT(21)
+#define CHCFG_SAD BIT(20)
+#define CHCFG_SEL(bits) ((bits) & 0x07)
+#define CHCFG_MEM_COPY (0x80400008)
+
+#define DCTRL_LVINT BIT(1)
+#define DCTRL_PR BIT(0)
+#define DCTRL_DEFAULT (DCTRL_LVINT | DCTRL_PR)
+
+/* LINK MODE DESCRIPTOR */
+#define HEADER_DIM BIT(3)
+#define HEADER_WBD BIT(2)
+#define HEADER_LE BIT(1)
+#define HEADER_LV BIT(0)
+
+#define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16
+#define DMAC_NR_LMDESC 64
+
+/* -----------------------------------------------------------------------------
+ * Device access
+ */
+
+static void rz_dmac_writel(struct rz_dmac_engine *rzdma, unsigned int val,
+ unsigned int offset)
+{
+ writel(val, rzdma->base + offset);
+}
+
+static void rz_dmac_ext_writel(struct rz_dmac_engine *rzdma, unsigned int val,
+ unsigned int offset)
+{
+ writel(val, rzdma->ext_base + offset);
+}
+
+static u32 rz_dmac_ext_readl(struct rz_dmac_engine *rzdma, unsigned int offset)
+{
+ return readl(rzdma->ext_base + offset);
+}
+
+static void rz_dmac_ch_writel(struct rz_dmac_channel *channel, unsigned int val,
+ unsigned int offset, int which)
+{
+ if (which)
+ writel(val, channel->ch_base + offset);
+ else
+ writel(val, channel->ch_cmn_base + offset);
+}
+
+static u32 rz_dmac_ch_readl(struct rz_dmac_channel *channel,
+ unsigned int offset, int which)
+{
+ if (which)
+ return readl(channel->ch_base + offset);
+ else
+ return readl(channel->ch_cmn_base + offset);
+}
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+static void rz_lmdesc_setup(struct rz_dmac_channel *channel,
+ struct rz_lmdesc *lmdesc)
+{
+ u32 nxla;
+
+ channel->lmdesc.base = lmdesc;
+ channel->lmdesc.head = lmdesc;
+ channel->lmdesc.tail = lmdesc;
+ channel->lmdesc.valid = 0;
+ nxla = channel->lmdesc.base_dma;
+ while (lmdesc < (channel->lmdesc.base + (DMAC_NR_LMDESC - 1))) {
+ lmdesc->header = 0;
+ nxla += sizeof(*lmdesc);
+ lmdesc->nxla = nxla;
+ lmdesc++;
+ }
+
+ lmdesc->header = 0;
+ lmdesc->nxla = channel->lmdesc.base_dma;
+}
+
+/* -----------------------------------------------------------------------------
+ * Descriptors submission
+ */
+
+static dma_cookie_t rz_dmac_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+ struct dma_chan *chan = tx->chan;
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ dma_cookie_t cookie;
+ unsigned long flags;
+
+ spin_lock_irqsave(&channel->lock, flags);
+ list_move_tail(channel->ld_free.next, &channel->ld_queue);
+ cookie = dma_cookie_assign(tx);
+ spin_unlock_irqrestore(&channel->lock, flags);
+
+ return cookie;
+}
+
+/* -----------------------------------------------------------------------------
+ * Descriptors preparation
+ */
+
+static void lmdesc_recycle(struct rz_dmac_channel *channel)
+{
+ struct rz_lmdesc *lmdesc = channel->lmdesc.head;
+
+ while (!(lmdesc->header & HEADER_LV)) {
+ lmdesc->header = 0;
+ channel->lmdesc.valid--;
+ lmdesc++;
+ if (lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
+ lmdesc = channel->lmdesc.base;
+ }
+ channel->lmdesc.head = lmdesc;
+}
+
+static void rz_dmac_enable_hw(struct rz_dmac_desc *d)
+{
+ struct dma_chan *chan = d->desc.chan;
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ unsigned long flags;
+ u32 nxla;
+ u32 chctrl;
+ u32 chstat;
+
+ dev_dbg(rzdma->dev, "%s channel %d\n", __func__, channel->index);
+
+ local_irq_save(flags);
+
+ lmdesc_recycle(channel);
+
+ nxla = channel->lmdesc.base_dma +
+ (sizeof(struct rz_lmdesc) * (channel->lmdesc.head -
+ channel->lmdesc.base));
+
+ chstat = rz_dmac_ch_readl(channel, CHSTAT, 1);
+ if (!(chstat & CHSTAT_EN)) {
+ chctrl = (channel->chctrl | CHCTRL_SETEN);
+ rz_dmac_ch_writel(channel, nxla, NXLA, 1);
+ rz_dmac_ch_writel(channel, channel->chcfg, CHCFG, 1);
+ rz_dmac_ch_writel(channel, CHCTRL_SWRST, CHCTRL, 1);
+ rz_dmac_ch_writel(channel, chctrl, CHCTRL, 1);
+ }
+
+ local_irq_restore(flags);
+}
+
+static void rz_dmac_disable_hw(struct rz_dmac_channel *channel)
+{
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ unsigned long flags;
+
+ dev_dbg(rzdma->dev, "%s channel %d\n", __func__, channel->index);
+
+ local_irq_save(flags);
+ rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
+ local_irq_restore(flags);
+}
+
+static void set_dmars_register(struct rz_dmac_engine *rzdma, int nr, u32 dmars)
+{
+ u32 dmars_offset = (nr / 2) * 4;
+ u32 dmars32;
+
+ dmars32 = rz_dmac_ext_readl(rzdma, dmars_offset);
+ if (nr % 2) {
+ dmars32 &= 0x0000ffff;
+ dmars32 |= dmars << 16;
+ } else {
+ dmars32 &= 0xffff0000;
+ dmars32 |= dmars;
+ }
+
+ rz_dmac_ext_writel(rzdma, dmars32, dmars_offset);
+}
+
+static const struct rz_dmac_slave_config *
+dma_find_slave(const struct rz_dmac_slave_config *slave, int slave_num,
+ u32 mid_rid)
+{
+ int i;
+
+ for (i = 0; i < slave_num; i++) {
+ const struct rz_dmac_slave_config *t = &slave[i];
+
+ if (mid_rid == t->mid_rid)
+ return t;
+ }
+
+ return NULL;
+}
+
+static void prepare_desc_for_memcpy(struct rz_dmac_desc *d)
+{
+ struct dma_chan *chan = d->desc.chan;
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ struct rz_lmdesc *lmdesc = channel->lmdesc.base;
+ u32 chcfg = CHCFG_MEM_COPY;
+ u32 dmars = 0;
+
+ lmdesc = channel->lmdesc.tail;
+
+ /* prepare descriptor */
+ lmdesc->sa = d->src;
+ lmdesc->da = d->dest;
+ lmdesc->tb = d->len;
+ lmdesc->chcfg = chcfg;
+ lmdesc->chitvl = 0;
+ lmdesc->chext = 0;
+ lmdesc->header = HEADER_LV;
+
+ set_dmars_register(rzdma, channel->index, dmars);
+
+ channel->chcfg = chcfg;
+ channel->chctrl = CHCTRL_STG | CHCTRL_SETEN;
+}
+
+static void prepare_descs_for_slave_sg(struct rz_dmac_desc *d)
+{
+ struct dma_chan *chan = d->desc.chan;
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ struct rz_lmdesc *lmdesc;
+ const struct rz_dmac_slave_config *slave = channel->slave;
+ struct scatterlist *sg, *sgl = d->sg;
+ unsigned int i, sg_len = d->sgcount;
+ u32 chcfg;
+
+ chcfg = channel->slave->chcfg | (CHCFG_SEL(channel->index) | CHCFG_DEM |
+ CHCFG_DMS);
+
+ if (d->direction == DMA_DEV_TO_MEM)
+ chcfg |= CHCFG_SAD;
+ else
+ chcfg |= CHCFG_DAD;
+
+ channel->chcfg = chcfg;
+ channel->per_address = slave->addr;
+
+ /* Prepare descriptors */
+ lmdesc = channel->lmdesc.tail;
+
+ for (i = 0, sg = sgl; i < sg_len; i++, sg = sg_next(sg)) {
+ if (d->direction == DMA_DEV_TO_MEM) {
+ lmdesc->sa = channel->per_address;
+ lmdesc->da = sg_dma_address(sg);
+ } else {
+ lmdesc->sa = sg_dma_address(sg);
+ lmdesc->da = channel->per_address;
+ }
+
+ lmdesc->tb = sg_dma_len(sg);
+ lmdesc->chitvl = 0;
+ lmdesc->chext = 0;
+ if (i == (sg_len - 1)) {
+ lmdesc->chcfg = (chcfg & ~CHCFG_DEM);
+ lmdesc->header = HEADER_LV;
+ } else {
+ lmdesc->chcfg = chcfg;
+ lmdesc->header = HEADER_LV;
+ }
+ if (++lmdesc >= (channel->lmdesc.base + DMAC_NR_LMDESC))
+ lmdesc = channel->lmdesc.base;
+ }
+
+ channel->lmdesc.tail = lmdesc;
+
+ set_dmars_register(rzdma, channel->index, slave->mid_rid);
+ channel->chctrl = CHCTRL_SETEN;
+}
+
+static int rz_dmac_xfer_desc(struct rz_dmac_desc *d)
+{
+ /* Configure and enable */
+ switch (d->type) {
+ case RZ_DMAC_DESC_MEMCPY:
+ prepare_desc_for_memcpy(d);
+ break;
+
+ case RZ_DMAC_DESC_SLAVE_SG:
+ prepare_descs_for_slave_sg(d);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+
+ rz_dmac_enable_hw(d);
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * DMA engine operations
+ */
+static int rz_dmac_alloc_chan_resources(struct dma_chan *chan)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ const struct rz_dmac_slave_config *slave = rzdma->slave;
+ const struct rz_dmac_slave_config *hit;
+ int slave_num = rzdma->slave_num;
+ u32 *mid_rid = chan->private;
+
+ if (mid_rid) {
+ hit = dma_find_slave(slave, slave_num, *mid_rid);
+ if (!hit)
+ return -ENODEV;
+ channel->slave = hit;
+ }
+
+ while (channel->descs_allocated < RZ_DMAC_MAX_CHAN_DESCRIPTORS) {
+ struct rz_dmac_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ break;
+ memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
+ dma_async_tx_descriptor_init(&desc->desc, chan);
+ desc->desc.tx_submit = rz_dmac_tx_submit;
+ desc->desc.flags = DMA_CTRL_ACK;
+ desc->status = DMA_COMPLETE;
+
+ list_add_tail(&desc->node, &channel->ld_free);
+ channel->descs_allocated++;
+ }
+
+ if (!channel->descs_allocated)
+ return -ENOMEM;
+
+ return channel->descs_allocated;
+}
+
+static struct dma_async_tx_descriptor *
+rz_dmac_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+ size_t len, unsigned long flags)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ struct rz_dmac_desc *desc;
+
+ dev_dbg(rzdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%ld\n",
+ __func__, channel->index, src, dest, len);
+
+ if (list_empty(&channel->ld_free))
+ return NULL;
+
+ desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
+
+ desc->type = RZ_DMAC_DESC_MEMCPY;
+ desc->src = src;
+ desc->dest = dest;
+ desc->len = len;
+ desc->direction = DMA_MEM_TO_MEM;
+ desc->desc.callback = NULL;
+ desc->desc.callback_param = NULL;
+
+ return &desc->desc;
+}
+
+static struct dma_async_tx_descriptor *
+rz_dmac_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
+ unsigned int sg_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct scatterlist *sg;
+ int i, dma_length = 0;
+ struct rz_dmac_desc *desc;
+
+ if (list_empty(&channel->ld_free))
+ return NULL;
+
+ desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ dma_length += sg_dma_len(sg);
+ }
+
+ desc->type = RZ_DMAC_DESC_SLAVE_SG;
+ desc->sg = sgl;
+ desc->sgcount = sg_len;
+ desc->len = dma_length;
+ desc->direction = direction;
+
+ if (direction == DMA_DEV_TO_MEM)
+ desc->src = channel->per_address;
+ else
+ desc->dest = channel->per_address;
+
+ desc->desc.callback = NULL;
+ desc->desc.callback_param = NULL;
+
+ return &desc->desc;
+}
+
+static int rz_dmac_config(struct dma_chan *chan,
+ struct dma_slave_config *config)
+{
+ struct rz_dmac_channel *rzdmac = to_rz_dmac_chan(chan);
+
+ if (config->direction == DMA_DEV_TO_MEM) {
+ rzdmac->per_address = config->src_addr;
+ rzdmac->word_size = config->src_addr_width;
+ } else {
+ rzdmac->per_address = config->dst_addr;
+ rzdmac->word_size = config->dst_addr_width;
+ }
+
+ return 0;
+}
+
+static void rz_dmac_free_chan_resources(struct dma_chan *chan)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_lmdesc *lmdesc = channel->lmdesc.base;
+ struct rz_dmac_desc *desc, *_desc;
+ unsigned long flags;
+ unsigned int i;
+
+ spin_lock_irqsave(&channel->lock, flags);
+
+ for (i = 0; i < DMAC_NR_LMDESC; i++)
+ lmdesc[i].header = 0;
+
+ rz_dmac_disable_hw(channel);
+ list_splice_tail_init(&channel->ld_active, &channel->ld_free);
+ list_splice_tail_init(&channel->ld_queue, &channel->ld_free);
+
+ spin_unlock_irqrestore(&channel->lock, flags);
+
+ list_for_each_entry_safe(desc, _desc, &channel->ld_free, node) {
+ kfree(desc);
+ channel->descs_allocated--;
+ }
+
+ INIT_LIST_HEAD(&channel->ld_free);
+}
+
+static int rz_dmac_terminate_all(struct dma_chan *chan)
+{
+ struct rz_dmac_channel *rzdmac = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = rzdmac->rzdma;
+ unsigned long flags;
+
+ rz_dmac_disable_hw(rzdmac);
+ spin_lock_irqsave(&rzdma->lock, flags);
+ list_splice_tail_init(&rzdmac->ld_active, &rzdmac->ld_free);
+ list_splice_tail_init(&rzdmac->ld_queue, &rzdmac->ld_free);
+ spin_unlock_irqrestore(&rzdma->lock, flags);
+
+ return 0;
+}
+
+static enum dma_status rz_dmac_tx_status(struct dma_chan *chan,
+ dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ return dma_cookie_status(chan, cookie, txstate);
+}
+
+static void rz_dmac_issue_pending(struct dma_chan *chan)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ struct rz_dmac_desc *desc;
+ unsigned long flags;
+
+ spin_lock_irqsave(&channel->lock, flags);
+
+ if (!list_empty(&channel->ld_queue)) {
+ desc = list_first_entry(&channel->ld_queue,
+ struct rz_dmac_desc, node);
+
+ if (rz_dmac_xfer_desc(desc) < 0) {
+ dev_warn(rzdma->dev, "ch: %d couldn't issue DMA xfer\n",
+ channel->index);
+ } else {
+ list_move_tail(channel->ld_queue.next,
+ &channel->ld_active);
+ }
+ }
+
+ spin_unlock_irqrestore(&channel->lock, flags);
+}
+
+/* -----------------------------------------------------------------------------
+ * IRQ handling
+ */
+
+static void dma_irq_handle_channel(struct rz_dmac_channel *channel)
+{
+ u32 chstat, chctrl;
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+
+ chstat = rz_dmac_ch_readl(channel, CHSTAT, 1);
+ if (chstat & CHSTAT_ER) {
+ dev_err(rzdma->dev, "DMAC err CHSTAT_%d = %08X\n",
+ channel->index, chstat);
+ rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
+ goto done;
+ }
+
+ chctrl = rz_dmac_ch_readl(channel, CHCTRL, 1);
+ rz_dmac_ch_writel(channel, chctrl | CHCTRL_CLREND, CHCTRL, 1);
+done:
+ return;
+}
+
+static irqreturn_t rz_dmac_irq_handler(int irq, void *dev_id)
+{
+ struct rz_dmac_channel *channel = dev_id;
+
+ if (channel) {
+ dma_irq_handle_channel(channel);
+ return IRQ_WAKE_THREAD;
+ }
+ /* handle DMAERR irq */
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t rz_dmac_irq_handler_thread(int irq, void *dev_id)
+{
+ struct rz_dmac_channel *channel = dev_id;
+ struct rz_dmac_desc *desc = NULL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&channel->lock, flags);
+
+ if (list_empty(&channel->ld_active)) {
+ /* Someone might have called terminate all */
+ goto out;
+ }
+
+ desc = list_first_entry(&channel->ld_active, struct rz_dmac_desc, node);
+
+ dma_cookie_complete(&desc->desc);
+ list_move_tail(channel->ld_active.next, &channel->ld_free);
+
+ if (!list_empty(&channel->ld_queue)) {
+ desc = list_first_entry(&channel->ld_queue, struct rz_dmac_desc,
+ node);
+ if (rz_dmac_xfer_desc(desc) == 0)
+ list_move_tail(channel->ld_queue.next,
+ &channel->ld_active);
+ }
+out:
+ spin_unlock_irqrestore(&channel->lock, flags);
+ if (desc)
+ dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
+
+ return IRQ_HANDLED;
+}
+
+/* -----------------------------------------------------------------------------
+ * OF xlate and channel filter
+ */
+
+static bool rz_dmac_chan_filter(struct dma_chan *chan, void *arg)
+{
+ struct rz_dmac_channel *channel = to_rz_dmac_chan(chan);
+ struct rz_dmac_engine *rzdma = channel->rzdma;
+ struct of_phandle_args *dma_spec = arg;
+ const struct rz_dmac_slave_config *hit;
+ u32 mid_rid = dma_spec->args[0];
+
+ hit = dma_find_slave(rzdma->slave, rzdma->slave_num, mid_rid);
+ if (hit)
+ channel->slave = hit;
+
+ return hit;
+}
+
+static struct dma_chan *rz_dmac_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ dma_cap_mask_t mask;
+
+ if (dma_spec->args_count != 1)
+ return NULL;
+
+ /* Only slave DMA channels can be allocated via DT */
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ return dma_request_channel(mask, rz_dmac_chan_filter, dma_spec);
+}
+
+/* -----------------------------------------------------------------------------
+ * Probe and remove
+ */
+
+static int rz_dmac_chan_probe(struct rz_dmac_engine *rzdma, unsigned int index)
+{
+ struct platform_device *pdev = to_platform_device(rzdma->dev);
+ struct rz_dmac_channel *channel = &rzdma->channel[index];
+ char pdev_irqname[5];
+ struct rz_lmdesc *lmdesc;
+ char *irqname;
+ int ret;
+
+ channel->rzdma = rzdma;
+ channel->index = index;
+
+ spin_lock_init(&channel->lock);
+
+ INIT_LIST_HEAD(&channel->ld_queue);
+ INIT_LIST_HEAD(&channel->ld_free);
+ INIT_LIST_HEAD(&channel->ld_active);
+
+ /* Request the channel interrupt. */
+ sprintf(pdev_irqname, "ch%u", index);
+ channel->irq = platform_get_irq_byname(pdev, pdev_irqname);
+ if (channel->irq < 0) {
+ dev_err(rzdma->dev, "no IRQ specified for channel %u\n", index);
+ return -ENODEV;
+ }
+
+ irqname = devm_kasprintf(rzdma->dev, GFP_KERNEL, "%s:%u",
+ dev_name(rzdma->dev), index);
+ if (!irqname)
+ return -ENOMEM;
+
+ ret = devm_request_threaded_irq(rzdma->dev, channel->irq,
+ rz_dmac_irq_handler,
+ rz_dmac_irq_handler_thread, 0,
+ irqname, channel);
+ if (ret) {
+ dev_err(rzdma->dev, "request IRQ failed%u (%d)\n",
+ channel->irq, ret);
+ return ret;
+ }
+
+ channel->chan.device = &rzdma->dma_device;
+ dma_cookie_init(&channel->chan);
+
+ /* Set io base address for each channel */
+ if (index < 8) {
+ channel->ch_base = rzdma->base + CHANNEL_0_7_OFFSET +
+ EACH_CHANNEL_OFFSET * index;
+ channel->ch_cmn_base = rzdma->base + CHANNEL_0_7_COMMON_BASE;
+ } else {
+ channel->ch_base = rzdma->base + CHANNEL_8_15_OFFSET +
+ EACH_CHANNEL_OFFSET * (index - 8);
+ channel->ch_cmn_base = rzdma->base + CHANNEL_8_15_COMMON_BASE;
+ }
+ /* Allocate descriptors */
+ lmdesc = dma_alloc_coherent(&pdev->dev,
+ sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
+ &channel->lmdesc.base_dma, GFP_KERNEL);
+ if (!lmdesc) {
+ dev_err(&pdev->dev, "Can't allocate memory (lmdesc)\n");
+ return -ENOMEM;
+ }
+ rz_lmdesc_setup(channel, lmdesc);
+
+ /* Add the channel to the DMAC list */
+ list_add_tail(&channel->chan.device_node,
+ &rzdma->dma_device.channels);
+
+ /* Initialize register for each channel */
+ rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
+
+ return 0;
+}
+
+#define RZ_DMAC_MAX_CHANNELS 16
+
+static int rz_dmac_parse_of(struct device *dev, struct rz_dmac_engine *rzdma)
+{
+ struct device_node *np = dev->of_node;
+ u32 *dmacfg;
+ int i = 0;
+ int n_slaves;
+ int ret;
+
+ ret = of_property_read_u32(np, "dma-channels", &rzdma->n_channels);
+ if (ret < 0) {
+ dev_err(dev, "unable to read dma-channels property\n");
+ return ret;
+ }
+
+ if (rzdma->n_channels <= 0 ||
+ rzdma->n_channels > RZ_DMAC_MAX_CHANNELS) {
+ dev_err(dev, "invalid number of channels %u\n",
+ rzdma->n_channels);
+ return -EINVAL;
+ }
+
+ n_slaves = of_property_count_elems_of_size(np,
+ "renesas,rz-dmac-slavecfg",
+ 3 * sizeof(u32));
+ if (n_slaves < 0) {
+ dev_warn(dev, "No setting for slave found or %s\n",
+ "rz-dmac-slavecfg property is not multiple of 3");
+ n_slaves = 0;
+ goto done;
+ }
+
+ rzdma->slave = devm_kzalloc(dev,
+ sizeof(struct rz_dmac_slave_config) * n_slaves,
+ GFP_KERNEL);
+ if (!rzdma->slave)
+ return -ENOMEM;
+
+ dmacfg = kcalloc(n_slaves, sizeof(u32), GFP_KERNEL);
+ if (!dmacfg)
+ return -ENOMEM;
+
+ if (of_property_read_u32_array(np, "renesas,rz-dmac-slavecfg",
+ dmacfg, n_slaves * 3)) {
+ dev_err(dev, "unable to read rz-dmac-slavecfg property\n");
+ kfree(dmacfg);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < n_slaves; i++) {
+ rzdma->slave[i].mid_rid = *dmacfg++;
+ rzdma->slave[i].addr = *dmacfg++;
+ rzdma->slave[i].chcfg = *dmacfg++;
+ }
+
+ kfree(dmacfg);
+done:
+ rzdma->slave_num = n_slaves;
+
+ return 0;
+}
+
+static int rz_dmac_probe(struct platform_device *pdev)
+{
+ const char *irqname = "error";
+ struct rz_dmac_engine *rzdma;
+ int channel_num;
+ int ret, i;
+ int irq;
+
+ rzdma = devm_kzalloc(&pdev->dev, sizeof(*rzdma), GFP_KERNEL);
+ if (!rzdma)
+ return -ENOMEM;
+
+ rzdma->dev = &pdev->dev;
+ rzdma->dma_device.dev = &pdev->dev;
+ platform_set_drvdata(pdev, rzdma);
+
+ ret = rz_dmac_parse_of(&pdev->dev, rzdma);
+ if (ret < 0)
+ return ret;
+
+ channel_num = rzdma->n_channels;
+
+ /* Request resources */
+ rzdma->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(rzdma->base))
+ return PTR_ERR(rzdma->base);
+
+ rzdma->ext_base = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(rzdma->ext_base))
+ return PTR_ERR(rzdma->ext_base);
+
+ /* Register interrupt handler for error */
+ irq = platform_get_irq_byname(pdev, irqname);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no error IRQ specified\n");
+ return -ENODEV;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, rz_dmac_irq_handler, 0,
+ irqname, NULL);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to request IRQ %u (%d)\n",
+ irq, ret);
+ return ret;
+ }
+
+ INIT_LIST_HEAD(&rzdma->dma_device.channels);
+ dma_cap_set(DMA_SLAVE, rzdma->dma_device.cap_mask);
+ dma_cap_set(DMA_MEMCPY, rzdma->dma_device.cap_mask);
+ spin_lock_init(&rzdma->lock);
+
+ rzdma->channel = devm_kzalloc(&pdev->dev,
+ sizeof(struct rz_dmac_channel) * channel_num,
+ GFP_KERNEL);
+ if (!rzdma->channel)
+ return -ENOMEM;
+
+ for (i = 0; i < channel_num; i++) {
+ ret = rz_dmac_chan_probe(rzdma, i);
+ if (ret < 0)
+ goto err;
+ }
+
+ /* Register the DMAC as a DMA provider for DT. */
+ if (of_dma_controller_register(pdev->dev.of_node, rz_dmac_of_xlate,
+ NULL) < 0)
+ dev_err(&pdev->dev, "unable to register as provider for DT\n");
+
+ /* Initialize register for all channels */
+ rz_dmac_writel(rzdma, DCTRL_DEFAULT, CHANNEL_0_7_COMMON_BASE + DCTRL);
+ rz_dmac_writel(rzdma, DCTRL_DEFAULT, CHANNEL_8_15_COMMON_BASE + DCTRL);
+
+ rzdma->dma_device.device_alloc_chan_resources = rz_dmac_alloc_chan_resources;
+ rzdma->dma_device.device_free_chan_resources = rz_dmac_free_chan_resources;
+ rzdma->dma_device.device_tx_status = rz_dmac_tx_status;
+ rzdma->dma_device.device_prep_slave_sg = rz_dmac_prep_slave_sg;
+ rzdma->dma_device.device_prep_dma_memcpy = rz_dmac_prep_dma_memcpy;
+ rzdma->dma_device.device_config = rz_dmac_config;
+ rzdma->dma_device.device_terminate_all = rz_dmac_terminate_all;
+ rzdma->dma_device.device_issue_pending = rz_dmac_issue_pending;
+
+ rzdma->dma_device.copy_align = 0;
+ rzdma->dma_device.dev->dma_parms = &rzdma->dma_parms;
+ dma_set_max_seg_size(rzdma->dma_device.dev, 0xffffff);
+
+ ret = dma_async_device_register(&rzdma->dma_device);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to register\n");
+ goto dma_register_err;
+ }
+ return 0;
+
+dma_register_err:
+ of_dma_controller_free(pdev->dev.of_node);
+err:
+ channel_num = i ? i - 1 : 0;
+ for (i = 0; i < channel_num; i++) {
+ struct rz_dmac_channel *channel = &rzdma->channel[i];
+
+ dma_free_coherent(NULL,
+ sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
+ channel->lmdesc.base,
+ channel->lmdesc.base_dma);
+ }
+
+ return ret;
+}
+
+static int rz_dmac_remove(struct platform_device *pdev)
+{
+ struct rz_dmac_engine *rzdma = platform_get_drvdata(pdev);
+ int i, channel_num = rzdma->n_channels;
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&rzdma->dma_device);
+
+ /* free allocated resources */
+ for (i = 0; i < channel_num; i++) {
+ struct rz_dmac_channel *channel = &rzdma->channel[i];
+
+ dma_free_coherent(NULL,
+ sizeof(struct rz_lmdesc) * DMAC_NR_LMDESC,
+ channel->lmdesc.base,
+ channel->lmdesc.base_dma);
+ }
+
+ return 0;
+}
+
+static const struct of_device_id of_rz_dmac_match[] = {
+ { .compatible = "renesas,rz-dmac", },
+ { /* Sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_rz_dmac_match);
+
+static struct platform_driver rz_dmac_driver = {
+ .driver = {
+ .name = "rz-dmac",
+ .of_match_table = of_rz_dmac_match,
+ },
+ .probe = rz_dmac_probe,
+ .remove = rz_dmac_remove,
+};
+
+module_platform_driver(rz_dmac_driver);
+
+MODULE_DESCRIPTION("Renesas RZ/G2L DMA Controller Driver");
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
@ 2021-06-11 17:55 ` Rob Herring
2021-06-12 12:17 ` Biju Das
2021-06-11 19:39 ` Rob Herring
2021-06-14 12:11 ` Geert Uytterhoeven
2 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2021-06-11 17:55 UTC (permalink / raw)
To: Biju Das
Cc: Prabhakar Mahadev Lad, devicetree, Chris Paterson, Vinod Koul,
linux-renesas-soc, Chris Brandt, Geert Uytterhoeven, Rob Herring,
dmaengine
On Fri, 11 Jun 2021 12:36:38 +0100, Biju Das wrote:
> Document RZ/G2L DMAC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/dma/renesas,rz-dmac.yaml | 132 ++++++++++++++++++
> 1 file changed, 132 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dts:20:18: fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
20 | #include <dt-bindings/clock/r9a07g044-cpg.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:380: Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1416: dt_binding_check] Error 2
\ndoc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1490917
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
2021-06-11 17:55 ` Rob Herring
@ 2021-06-11 19:39 ` Rob Herring
2021-06-12 12:26 ` Biju Das
2021-06-14 12:11 ` Geert Uytterhoeven
2 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2021-06-11 19:39 UTC (permalink / raw)
To: Biju Das
Cc: Vinod Koul, Chris Brandt, dmaengine, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
On Fri, Jun 11, 2021 at 12:36:38PM +0100, Biju Das wrote:
> Document RZ/G2L DMAC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> .../bindings/dma/renesas,rz-dmac.yaml | 132 ++++++++++++++++++
> 1 file changed, 132 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> new file mode 100644
> index 000000000000..df54bd6ddfd4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L DMA Controller
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> + - const: renesas,rz-dmac
> +
> + reg:
> + items:
> + - description: Control and channel register block
> + - description: DMA extension resource selector block
> +
> + interrupts:
> + maxItems: 17
> +
> + interrupt-names:
> + maxItems: 17
> + items:
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
> + - pattern: "^ch([0-9]|1[0-5])$"
Is there some reason these need be in undefined order?
> + - const: error
> +
> + clocks:
> + maxItems: 1
> +
> + '#dma-cells':
> + const: 1
> + description:
> + The cell specifies the MID/RID of the DMAC port connected to
> + the DMA client.
> +
> + dma-channels:
> + const: 16
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + renesas,rz-dmac-slavecfg:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + DMA configuration for a slave channel. Each channel must have an array of
> + 3 items as below.
> + first item in the array is MID+RID
> + second item in the array is slave src or dst address
> + third item in the array is channel configuration value.
Why not put all these in the dma-cells? You already have 1 of them.
Though doesn't the client device know what address to use?
> + items:
> + minItems: 3
> + maxItems: 48
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> + - clocks
> + - '#dma-cells'
> + - dma-channels
> + - power-domains
> + - resets
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> + dmac: dma-controller@11820000 {
> + compatible = "renesas,dmac-r9a07g044",
> + "renesas,rz-dmac";
> + reg = <0x11820000 0x10000>,
> + <0x11830000 0x10000>;
> + interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "ch0", "ch1", "ch2", "ch3",
> + "ch4", "ch5", "ch6", "ch7",
> + "ch8", "ch9", "ch10", "ch11",
> + "ch12", "ch13", "ch14", "ch15",
> + "error";
> + clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
> + power-domains = <&cpg>;
> + resets = <&cpg R9A07G044_CLK_DMAC>;
> + #dma-cells = <1>;
> + dma-channels = <16>;
> + renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
> + };
> --
> 2.17.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 17:55 ` Rob Herring
@ 2021-06-12 12:17 ` Biju Das
0 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2021-06-12 12:17 UTC (permalink / raw)
To: Rob Herring
Cc: Prabhakar Mahadev Lad, devicetree, Chris Paterson, Vinod Koul,
linux-renesas-soc, Chris Brandt, Geert Uytterhoeven, Rob Herring,
dmaengine
Hi Rob,
Thanks for the review.
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> On Fri, 11 Jun 2021 12:36:38 +0100, Biju Das wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../bindings/dma/renesas,rz-dmac.yaml | 132 ++++++++++++++++++
> > 1 file changed, 132 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dts:20:18:
> fatal error: dt-bindings/clock/r9a07g044-cpg.h: No such file or directory
> 20 | #include <dt-bindings/clock/r9a07g044-cpg.h>
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> compilation terminated.
> make[1]: *** [scripts/Makefile.lib:380:
> Documentation/devicetree/bindings/dma/renesas,rz-dmac.example.dt.yaml]
> Error 1
> make[1]: *** Waiting for unfinished jobs....
> make: *** [Makefile:1416: dt_binding_check] Error 2 \ndoc reference errors
> (make refcheckdocs):
>
> See
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.ozlabs.org%2Fpatch%2F1490917&data=04%7C01%7Cbiju.das.jz%40bp.renesas
> .com%7C0b0cf26acc004dba607508d92d0222fe%7C53d82571da1947e49cb4625a166a4a2a
> %7C0%7C0%7C637590309476730777%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAi
> LCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=lZ%2F0v9D4
> 9djAW8E4sA3zcHOFs4x%2F073f40FkAGZJ0ZI%3D&reserved=0
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
Sorry, The dependency patch is just queued. Next time, I will make sure
dependency patch is in the most recent rc1 before posting.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Sure will check and re-submit.
Regards,
Biju
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 19:39 ` Rob Herring
@ 2021-06-12 12:26 ` Biju Das
0 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2021-06-12 12:26 UTC (permalink / raw)
To: Rob Herring
Cc: Vinod Koul, Chris Brandt, dmaengine, devicetree,
Geert Uytterhoeven, Chris Paterson, Prabhakar Mahadev Lad,
linux-renesas-soc
Hi Rob,
Thanks for the feedback.
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> On Fri, Jun 11, 2021 at 12:36:38PM +0100, Biju Das wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > .../bindings/dma/renesas,rz-dmac.yaml | 132 ++++++++++++++++++
> > 1 file changed, 132 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > new file mode 100644
> > index 000000000000..df54bd6ddfd4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=04%7C
> > +01%7Cbiju.das.jz%40bp.renesas.com%7Ce46660b298b942937fe408d92d109c19%
> > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637590371623792000%7CUnk
> > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > +wiLCJXVCI6Mn0%3D%7C1000&sdata=kirztzPuCmsjeKEivOgQZqP5obsByrSaTnQ
> > +bzQbU%2BRM%3D&reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7Ce46660b298b942937fe408d92d109c19%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637590371623792000%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&sdata=U2lrBvVVhySXVYHK6Qk41VTGijep8yPaTCMJpSjRsXs%3D&am
> > +p;reserved=0
> > +
> > +title: Renesas RZ/G2L DMA Controller
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > + - const: renesas,rz-dmac
> > +
> > + reg:
> > + items:
> > + - description: Control and channel register block
> > + - description: DMA extension resource selector block
> > +
> > + interrupts:
> > + maxItems: 17
> > +
> > + interrupt-names:
> > + maxItems: 17
> > + items:
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
> > + - pattern: "^ch([0-9]|1[0-5])$"
>
> Is there some reason these need be in undefined order?
No. I will make it as defined order in next version.
>
> > + - const: error
> > +
> > + clocks:
> > + maxItems: 1
> > +
> > + '#dma-cells':
> > + const: 1
> > + description:
> > + The cell specifies the MID/RID of the DMAC port connected to
> > + the DMA client.
> > +
> > + dma-channels:
> > + const: 16
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + resets:
> > + maxItems: 1
> > +
> > + renesas,rz-dmac-slavecfg:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description: |
> > + DMA configuration for a slave channel. Each channel must have an
> array of
> > + 3 items as below.
> > + first item in the array is MID+RID
> > + second item in the array is slave src or dst address
> > + third item in the array is channel configuration value.
>
> Why not put all these in the dma-cells? You already have 1 of them.
Thanks for the suggestion. I will make use of dma-cells and will remove the above property
in next revision. Basically It simplifies the implementation as well.
> Though doesn't the client device know what address to use?
Indeed. it knows.
Cheers,
Biju
>
> > + items:
> > + minItems: 3
> > + maxItems: 48
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - '#dma-cells'
> > + - dma-channels
> > + - power-domains
> > + - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > + dmac: dma-controller@11820000 {
> > + compatible = "renesas,dmac-r9a07g044",
> > + "renesas,rz-dmac";
> > + reg = <0x11820000 0x10000>,
> > + <0x11830000 0x10000>;
> > + interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
> > + <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "ch0", "ch1", "ch2", "ch3",
> > + "ch4", "ch5", "ch6", "ch7",
> > + "ch8", "ch9", "ch10", "ch11",
> > + "ch12", "ch13", "ch14", "ch15",
> > + "error";
> > + clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
> > + power-domains = <&cpg>;
> > + resets = <&cpg R9A07G044_CLK_DMAC>;
> > + #dma-cells = <1>;
> > + dma-channels = <16>;
> > + renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
> > + };
> > --
> > 2.17.1
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
2021-06-11 17:55 ` Rob Herring
2021-06-11 19:39 ` Rob Herring
@ 2021-06-14 12:11 ` Geert Uytterhoeven
2021-06-14 12:54 ` Biju Das
2 siblings, 1 reply; 19+ messages in thread
From: Geert Uytterhoeven @ 2021-06-14 12:11 UTC (permalink / raw)
To: Biju Das
Cc: Vinod Koul, Rob Herring, Chris Brandt, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas,
Laurent Pinchart
Hi Biju,
On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Document RZ/G2L DMAC bindings.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L DMA Controller
> +
> +maintainers:
> + - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +allOf:
> + - $ref: "dma-controller.yaml#"
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
Please use "renesas,r9a07g044-dmac".
> + - const: renesas,rz-dmac
Does this need many changes for RZ/A1H and RZ/A2M?
> + renesas,rz-dmac-slavecfg:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: |
> + DMA configuration for a slave channel. Each channel must have an array of
> + 3 items as below.
> + first item in the array is MID+RID
Already in dmas.
> + second item in the array is slave src or dst address
As pointed out by Rob, already known by the slave driver.
> + third item in the array is channel configuration value.
What exactly is this?
Does the R-Car DMAC have this too? If yes, how does its driver handle it?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 12:11 ` Geert Uytterhoeven
@ 2021-06-14 12:54 ` Biju Das
2021-06-14 14:29 ` Laurent Pinchart
0 siblings, 1 reply; 19+ messages in thread
From: Biju Das @ 2021-06-14 12:54 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Vinod Koul, Rob Herring, Chris Brandt, dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas,
Laurent Pinchart
Hi Geert,
Thanks for the feedback.
> -----Original Message-----
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> Hi Biju,
>
> On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -0,0 +1,132 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=04%7C
> > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%
> > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnk
> > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDejp8wo
> > +Nrx9iO0ht8%3D&reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw%3D&
> > +amp;reserved=0
> > +
> > +title: Renesas RZ/G2L DMA Controller
> > +
> > +maintainers:
> > + - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +allOf:
> > + - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
>
> Please use "renesas,r9a07g044-dmac".
OK. Will change.
> > + - const: renesas,rz-dmac
>
> Does this need many changes for RZ/A1H and RZ/A2M?
It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
There is some difference in MID bit size. Other wise both identical.
> > + renesas,rz-dmac-slavecfg:
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > + description: |
> > + DMA configuration for a slave channel. Each channel must have an
> array of
> > + 3 items as below.
> > + first item in the array is MID+RID
>
> Already in dmas.
>
> > + second item in the array is slave src or dst address
>
> As pointed out by Rob, already known by the slave driver.
>
> > + third item in the array is channel configuration value.
>
> What exactly is this?
> Does the R-Car DMAC have this too? If yes, how does its driver handle it?
On R-CAR DMAC, we have only MID + RID values. Where as here we have channel configuration value With different set of parameter as mentioned in Table 16.4.
Please see Page 569, Table 16.4 On-Chip Module requests section.
For eg:- as per Rob's suggestion, I have modelled the driver with the below entries in ALSA driver for playback/record use case.
dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
<&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
dma-names = "tx", "rx";
Using first parameter, it gets dmac channel. using second and third parameter it configures
the channel.
Regards,
Biju
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 12:54 ` Biju Das
@ 2021-06-14 14:29 ` Laurent Pinchart
2021-06-14 16:09 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Laurent Pinchart @ 2021-06-14 14:29 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > -----Original Message-----
> > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> >
> > Hi Biju,
> >
> > On Fri, Jun 11, 2021 at 1:36 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Document RZ/G2L DMAC bindings.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Thanks for your patch!
> >
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > @@ -0,0 +1,132 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > > +---
> > > +$id:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=04%7C
> > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%
> > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnk
> > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDejp8wo
> > > +Nrx9iO0ht8%3D&reserved=0
> > > +$schema:
> > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571da19
> > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWFpbGZ
> > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw%3D&
> > > +amp;reserved=0
*sigh*
> > > +
> > > +title: Renesas RZ/G2L DMA Controller
> > > +
> > > +maintainers:
> > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > +
> > > +allOf:
> > > + - $ref: "dma-controller.yaml#"
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> >
> > Please use "renesas,r9a07g044-dmac".
>
> OK. Will change.
>
> > > + - const: renesas,rz-dmac
> >
> > Does this need many changes for RZ/A1H and RZ/A2M?
>
> It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> There is some difference in MID bit size. Other wise both identical.
>
>
> > > + renesas,rz-dmac-slavecfg:
> > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + description: |
> > > + DMA configuration for a slave channel. Each channel must have an
> > array of
> > > + 3 items as below.
> > > + first item in the array is MID+RID
> >
> > Already in dmas.
> >
> > > + second item in the array is slave src or dst address
> >
> > As pointed out by Rob, already known by the slave driver.
> >
> > > + third item in the array is channel configuration value.
> >
> > What exactly is this?
What would prevent the DMA client from passing the configuration to the
DMA channel through the DMA engine API, just like it passes the slave
source or destination address ?
> > Does the R-Car DMAC have this too? If yes, how does its driver handle it?
>
> On R-CAR DMAC, we have only MID + RID values. Where as here we have channel configuration value With different set of parameter as mentioned in Table 16.4.
>
> Please see Page 569, Table 16.4 On-Chip Module requests section.
>
> For eg:- as per Rob's suggestion, I have modelled the driver with the below entries in ALSA driver for playback/record use case.
>
> dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> dma-names = "tx", "rx";
>
> Using first parameter, it gets dmac channel. using second and third parameter it configures
> the channel.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 14:29 ` Laurent Pinchart
@ 2021-06-14 16:09 ` Biju Das
2021-06-14 16:17 ` Laurent Pinchart
0 siblings, 1 reply; 19+ messages in thread
From: Biju Das @ 2021-06-14 16:09 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > -----Original Message-----
> > > Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
> > >
> > > Hi Biju,
> > >
> > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > Document RZ/G2L DMAC bindings.
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > Reviewed-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Thanks for your patch!
> > >
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > @@ -0,0 +1,132 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=0
> > > > +4%7C
> > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da
> > > > +0c0%
> > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7
> > > > +CUnk
> > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > > +1haW
> > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDej
> > > > +p8wo
> > > > +Nrx9iO0ht8%3D&reserved=0
> > > > +$schema:
> > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > +devi
> > > > +cetree.org%2Fmeta-
> schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571
> > > > +da19
> > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWF
> > > > +pbGZ
> > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > +Mn0%
> > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw
> > > > +%3D&
> > > > +amp;reserved=0
>
> *sigh*
>
> > > > +
> > > > +title: Renesas RZ/G2L DMA Controller
> > > > +
> > > > +maintainers:
> > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > +
> > > > +allOf:
> > > > + - $ref: "dma-controller.yaml#"
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > >
> > > Please use "renesas,r9a07g044-dmac".
> >
> > OK. Will change.
> >
> > > > + - const: renesas,rz-dmac
> > >
> > > Does this need many changes for RZ/A1H and RZ/A2M?
> >
> > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't
> have the board.
> > There is some difference in MID bit size. Other wise both identical.
> >
> >
> > > > + renesas,rz-dmac-slavecfg:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > + description: |
> > > > + DMA configuration for a slave channel. Each channel must
> > > > + have an
> > > array of
> > > > + 3 items as below.
> > > > + first item in the array is MID+RID
> > >
> > > Already in dmas.
> > >
> > > > + second item in the array is slave src or dst address
> > >
> > > As pointed out by Rob, already known by the slave driver.
> > >
> > > > + third item in the array is channel configuration value.
> > >
> > > What exactly is this?
>
> What would prevent the DMA client from passing the configuration to the
> DMA channel through the DMA engine API, just like it passes the slave
> source or destination address ?
On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
The only way we can distinguish it is from channel configuration value.
Cheers,
Biju
>
> > > Does the R-Car DMAC have this too? If yes, how does its driver handle
> it?
> >
> > On R-CAR DMAC, we have only MID + RID values. Where as here we have
> channel configuration value With different set of parameter as mentioned
> in Table 16.4.
> >
> > Please see Page 569, Table 16.4 On-Chip Module requests section.
> >
> > For eg:- as per Rob's suggestion, I have modelled the driver with the
> below entries in ALSA driver for playback/record use case.
> >
> > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > <&dmac 0x256 0x10049c1c
> > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > dma-names = "tx", "rx";
> >
> > Using first parameter, it gets dmac channel. using second and third
> > parameter it configures the channel.
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 16:09 ` Biju Das
@ 2021-06-14 16:17 ` Laurent Pinchart
2021-06-14 16:24 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Laurent Pinchart @ 2021-06-14 16:17 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > Document RZ/G2L DMAC bindings.
> > > > >
> > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Thanks for your patch!
> > > >
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > > @@ -0,0 +1,132 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > > +1.2
> > > > > +---
> > > > > +$id:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > > +devi
> > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&data=0
> > > > > +4%7C
> > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da
> > > > > +0c0%
> > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7
> > > > > +CUnk
> > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik
> > > > > +1haW
> > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtzuDej
> > > > > +p8wo
> > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > +$schema:
> > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2F
> > > > > +devi
> > > > > +cetree.org%2Fmeta-
> > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d82571
> > > > > +da19
> > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7CTWF
> > > > > +pbGZ
> > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6
> > > > > +Mn0%
> > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnhJraw
> > > > > +%3D&
> > > > > +amp;reserved=0
> >
> > *sigh*
> >
> > > > > +
> > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > +
> > > > > +maintainers:
> > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > +
> > > > > +allOf:
> > > > > + - $ref: "dma-controller.yaml#"
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > >
> > > > Please use "renesas,r9a07g044-dmac".
> > >
> > > OK. Will change.
> > >
> > > > > + - const: renesas,rz-dmac
> > > >
> > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > >
> > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > There is some difference in MID bit size. Other wise both identical.
> > >
> > > > > + renesas,rz-dmac-slavecfg:
> > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > + description: |
> > > > > + DMA configuration for a slave channel. Each channel must
> > > > > + have an array of
> > > > > + 3 items as below.
> > > > > + first item in the array is MID+RID
> > > >
> > > > Already in dmas.
> > > >
> > > > > + second item in the array is slave src or dst address
> > > >
> > > > As pointed out by Rob, already known by the slave driver.
> > > >
> > > > > + third item in the array is channel configuration value.
> > > >
> > > > What exactly is this?
> >
> > What would prevent the DMA client from passing the configuration to the
> > DMA channel through the DMA engine API, just like it passes the slave
> > source or destination address ?
>
> On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
> The only way we can distinguish it is from channel configuration value.
Are those two different hardware DMA channels ? And configuration values
change between the two ?
> > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > handle it?
> > >
> > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > have channel configuration value With different set of parameter
> > > as mentioned in Table 16.4.
> > >
> > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > >
> > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > the below entries in ALSA driver for playback/record use case.
> > >
> > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > <&dmac 0x256 0x10049c1c
> > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > dma-names = "tx", "rx";
> > >
> > > Using first parameter, it gets dmac channel. using second and third
> > > parameter it configures the channel.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 16:17 ` Laurent Pinchart
@ 2021-06-14 16:24 ` Biju Das
2021-06-14 16:28 ` Laurent Pinchart
0 siblings, 1 reply; 19+ messages in thread
From: Biju Das @ 2021-06-14 16:24 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Laurent,
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> Hi Biju,
>
> On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > Document RZ/G2L DMAC bindings.
> > > > > >
> > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > Reviewed-by: Lad Prabhakar
> > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > >
> > > > > Thanks for your patch!
> > > > >
> > > > > > --- /dev/null
> > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.ya
> > > > > > +++ ml
> > > > > > @@ -0,0 +1,132 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML
> > > > > > +1.2
> > > > > > +---
> > > > > > +$id:
> > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > +F%2F
> > > > > > +devi
> > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&da
> > > > > > +ta=0
> > > > > > +4%7C
> > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92
> > > > > > +f2da
> > > > > > +0c0%
> > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6375926952868468
> > > > > > +09%7
> > > > > > +CUnk
> > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
> > > > > > +I6Ik
> > > > > > +1haW
> > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtz
> > > > > > +uDej
> > > > > > +p8wo
> > > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > > +$schema:
> > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > +F%2F
> > > > > > +devi
> > > > > > +cetree.org%2Fmeta-
> > > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d8
> > > > > > +2571
> > > > > > +da19
> > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7
> > > > > > +CTWF
> > > > > > +pbGZ
> > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> > > > > > +VCI6
> > > > > > +Mn0%
> > > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnh
> > > > > > +Jraw
> > > > > > +%3D&
> > > > > > +amp;reserved=0
> > >
> > > *sigh*
> > >
> > > > > > +
> > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > +
> > > > > > +maintainers:
> > > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > +
> > > > > > +allOf:
> > > > > > + - $ref: "dma-controller.yaml#"
> > > > > > +
> > > > > > +properties:
> > > > > > + compatible:
> > > > > > + items:
> > > > > > + - enum:
> > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > > >
> > > > > Please use "renesas,r9a07g044-dmac".
> > > >
> > > > OK. Will change.
> > > >
> > > > > > + - const: renesas,rz-dmac
> > > > >
> > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > >
> > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I
> don't have the board.
> > > > There is some difference in MID bit size. Other wise both identical.
> > > >
> > > > > > + renesas,rz-dmac-slavecfg:
> > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > + description: |
> > > > > > + DMA configuration for a slave channel. Each channel
> > > > > > + must have an array of
> > > > > > + 3 items as below.
> > > > > > + first item in the array is MID+RID
> > > > >
> > > > > Already in dmas.
> > > > >
> > > > > > + second item in the array is slave src or dst address
> > > > >
> > > > > As pointed out by Rob, already known by the slave driver.
> > > > >
> > > > > > + third item in the array is channel configuration value.
> > > > >
> > > > > What exactly is this?
> > >
> > > What would prevent the DMA client from passing the configuration to
> > > the DMA channel through the DMA engine API, just like it passes the
> > > slave source or destination address ?
> >
> > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx
> and rx.
> > The only way we can distinguish it is from channel configuration value.
>
> Are those two different hardware DMA channels ? And configuration values
> change between the two ?
Yes, REQD is different, apart from this Rx have transfer source and Tx have Transfer destination.
This particular SSIF ch2 is used only for half duplex compared to other SSIF channels.
Regards,
Biju
>
> > > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > > handle it?
> > > >
> > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > have channel configuration value With different set of parameter
> > > > as mentioned in Table 16.4.
> > > >
> > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > >
> > > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > > the below entries in ALSA driver for playback/record use case.
> > > >
> > > > dmas = <&dmac 0x255 0x10049c18
> CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > <&dmac 0x256 0x10049c1c
> > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > dma-names = "tx", "rx";
> > > >
> > > > Using first parameter, it gets dmac channel. using second and
> > > > third parameter it configures the channel.
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 16:24 ` Biju Das
@ 2021-06-14 16:28 ` Laurent Pinchart
2021-06-14 16:33 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Laurent Pinchart @ 2021-06-14 16:28 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > >
> > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > Reviewed-by: Lad Prabhakar
> > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > >
> > > > > > Thanks for your patch!
> > > > > >
> > > > > > > --- /dev/null
> > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.ya
> > > > > > > +++ ml
> > > > > > > @@ -0,0 +1,132 @@
> > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > +%YAML
> > > > > > > +1.2
> > > > > > > +---
> > > > > > > +$id:
> > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > > +F%2F
> > > > > > > +devi
> > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&da
> > > > > > > +ta=0
> > > > > > > +4%7C
> > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92
> > > > > > > +f2da
> > > > > > > +0c0%
> > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6375926952868468
> > > > > > > +09%7
> > > > > > > +CUnk
> > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
> > > > > > > +I6Ik
> > > > > > > +1haW
> > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCcrNtz
> > > > > > > +uDej
> > > > > > > +p8wo
> > > > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > > > +$schema:
> > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2
> > > > > > > +F%2F
> > > > > > > +devi
> > > > > > > +cetree.org%2Fmeta-
> > > > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C53d8
> > > > > > > +2571
> > > > > > > +da19
> > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnknown%7
> > > > > > > +CTWF
> > > > > > > +pbGZ
> > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJX
> > > > > > > +VCI6
> > > > > > > +Mn0%
> > > > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIAdLnh
> > > > > > > +Jraw
> > > > > > > +%3D&
> > > > > > > +amp;reserved=0
> > > >
> > > > *sigh*
> > > >
> > > > > > > +
> > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > +
> > > > > > > +maintainers:
> > > > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > +
> > > > > > > +allOf:
> > > > > > > + - $ref: "dma-controller.yaml#"
> > > > > > > +
> > > > > > > +properties:
> > > > > > > + compatible:
> > > > > > > + items:
> > > > > > > + - enum:
> > > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > > > >
> > > > > > Please use "renesas,r9a07g044-dmac".
> > > > >
> > > > > OK. Will change.
> > > > >
> > > > > > > + - const: renesas,rz-dmac
> > > > > >
> > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > >
> > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > > > There is some difference in MID bit size. Other wise both identical.
> > > > >
> > > > > > > + renesas,rz-dmac-slavecfg:
> > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > + description: |
> > > > > > > + DMA configuration for a slave channel. Each channel
> > > > > > > + must have an array of
> > > > > > > + 3 items as below.
> > > > > > > + first item in the array is MID+RID
> > > > > >
> > > > > > Already in dmas.
> > > > > >
> > > > > > > + second item in the array is slave src or dst address
> > > > > >
> > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > >
> > > > > > > + third item in the array is channel configuration value.
> > > > > >
> > > > > > What exactly is this?
> > > >
> > > > What would prevent the DMA client from passing the configuration to
> > > > the DMA channel through the DMA engine API, just like it passes the
> > > > slave source or destination address ?
> > >
> > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
> > > The only way we can distinguish it is from channel configuration value.
> >
> > Are those two different hardware DMA channels ? And configuration values
> > change between the two ?
>
> Yes, REQD is different, apart from this Rx have transfer source and Tx have Transfer destination.
> This particular SSIF ch2 is used only for half duplex compared to other SSIF channels.
Does this mean there's a single DMA channel, used by two clients, but
not at the same time as it only supports half-duplex ?
> > > > > > Does the R-Car DMAC have this too? If yes, how does its driver
> > > > > > handle it?
> > > > >
> > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > have channel configuration value With different set of parameter
> > > > > as mentioned in Table 16.4.
> > > > >
> > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > >
> > > > > For eg:- as per Rob's suggestion, I have modelled the driver with
> > > > > the below entries in ALSA driver for playback/record use case.
> > > > >
> > > > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > <&dmac 0x256 0x10049c1c
> > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > dma-names = "tx", "rx";
> > > > >
> > > > > Using first parameter, it gets dmac channel. using second and
> > > > > third parameter it configures the channel.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 16:28 ` Laurent Pinchart
@ 2021-06-14 16:33 ` Biju Das
2021-06-14 17:30 ` Laurent Pinchart
0 siblings, 1 reply; 19+ messages in thread
From: Biju Das @ 2021-06-14 16:33 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Laurent,
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> Hi Biju,
>
> On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > > >
> > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > Reviewed-by: Lad Prabhakar
> > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > >
> > > > > > > Thanks for your patch!
> > > > > > >
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dma
> > > > > > > > +++ c.ya
> > > > > > > > +++ ml
> > > > > > > > @@ -0,0 +1,132 @@
> > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > +%YAML
> > > > > > > > +1.2
> > > > > > > > +---
> > > > > > > > +$id:
> > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > +3A%2
> > > > > > > > +F%2F
> > > > > > > > +devi
> > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&am
> > > > > > > > +p;da
> > > > > > > > +ta=0
> > > > > > > > +4%7C
> > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d850
> > > > > > > > +8d92
> > > > > > > > +f2da
> > > > > > > > +0c0%
> > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286
> > > > > > > > +8468
> > > > > > > > +09%7
> > > > > > > > +CUnk
> > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > > > > > > > +JBTi
> > > > > > > > +I6Ik
> > > > > > > > +1haW
> > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCc
> > > > > > > > +rNtz
> > > > > > > > +uDej
> > > > > > > > +p8wo
> > > > > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > > > > +$schema:
> > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > +3A%2
> > > > > > > > +F%2F
> > > > > > > > +devi
> > > > > > > > +cetree.org%2Fmeta-
> > > > > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C
> > > > > > > > +53d8
> > > > > > > > +2571
> > > > > > > > +da19
> > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnkno
> > > > > > > > +wn%7
> > > > > > > > +CTWF
> > > > > > > > +pbGZ
> > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > > > > > > > +LCJX
> > > > > > > > +VCI6
> > > > > > > > +Mn0%
> > > > > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIA
> > > > > > > > +dLnh
> > > > > > > > +Jraw
> > > > > > > > +%3D&
> > > > > > > > +amp;reserved=0
> > > > >
> > > > > *sigh*
> > > > >
> > > > > > > > +
> > > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > > +
> > > > > > > > +maintainers:
> > > > > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > +
> > > > > > > > +allOf:
> > > > > > > > + - $ref: "dma-controller.yaml#"
> > > > > > > > +
> > > > > > > > +properties:
> > > > > > > > + compatible:
> > > > > > > > + items:
> > > > > > > > + - enum:
> > > > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > > > > >
> > > > > > > Please use "renesas,r9a07g044-dmac".
> > > > > >
> > > > > > OK. Will change.
> > > > > >
> > > > > > > > + - const: renesas,rz-dmac
> > > > > > >
> > > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > > >
> > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since
> I don't have the board.
> > > > > > There is some difference in MID bit size. Other wise both
> identical.
> > > > > >
> > > > > > > > + renesas,rz-dmac-slavecfg:
> > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > > + description: |
> > > > > > > > + DMA configuration for a slave channel. Each channel
> > > > > > > > + must have an array of
> > > > > > > > + 3 items as below.
> > > > > > > > + first item in the array is MID+RID
> > > > > > >
> > > > > > > Already in dmas.
> > > > > > >
> > > > > > > > + second item in the array is slave src or dst
> > > > > > > > + address
> > > > > > >
> > > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > > >
> > > > > > > > + third item in the array is channel configuration
> value.
> > > > > > >
> > > > > > > What exactly is this?
> > > > >
> > > > > What would prevent the DMA client from passing the configuration
> > > > > to the DMA channel through the DMA engine API, just like it
> > > > > passes the slave source or destination address ?
> > > >
> > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both
> tx and rx.
> > > > The only way we can distinguish it is from channel configuration
> value.
> > >
> > > Are those two different hardware DMA channels ? And configuration
> > > values change between the two ?
> >
> > Yes, REQD is different, apart from this Rx have transfer source and Tx
> have Transfer destination.
> > This particular SSIF ch2 is used only for half duplex compared to other
> SSIF channels.
>
> Does this mean there's a single DMA channel, used by two clients, but not
> at the same time as it only supports half-duplex ?
From hardware perspective, it is 2 channel. For eg:- playback/recording use case.
You cannot do simultaneous playback, but you can do playback or record separately.
Cheers,
Biju
> > > > > > > Does the R-Car DMAC have this too? If yes, how does its
> > > > > > > driver handle it?
> > > > > >
> > > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > > have channel configuration value With different set of
> > > > > > parameter as mentioned in Table 16.4.
> > > > > >
> > > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > > >
> > > > > > For eg:- as per Rob's suggestion, I have modelled the driver
> > > > > > with the below entries in ALSA driver for playback/record use
> case.
> > > > > >
> > > > > > dmas = <&dmac 0x255 0x10049c18
> CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > > <&dmac 0x256 0x10049c1c
> > > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > > dma-names = "tx", "rx";
> > > > > >
> > > > > > Using first parameter, it gets dmac channel. using second and
> > > > > > third parameter it configures the channel.
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 16:33 ` Biju Das
@ 2021-06-14 17:30 ` Laurent Pinchart
2021-06-15 8:06 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Laurent Pinchart @ 2021-06-14 17:30 UTC (permalink / raw)
To: Biju Das
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Biju,
On Mon, Jun 14, 2021 at 04:33:03PM +0000, Biju Das wrote:
> > On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > > > >
> > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > >
> > > > > > > > Thanks for your patch!
> > > > > > > >
> > > > > > > > > --- /dev/null
> > > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dma
> > > > > > > > > +++ c.ya
> > > > > > > > > +++ ml
> > > > > > > > > @@ -0,0 +1,132 @@
> > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > > +%YAML
> > > > > > > > > +1.2
> > > > > > > > > +---
> > > > > > > > > +$id:
> > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > > +3A%2
> > > > > > > > > +F%2F
> > > > > > > > > +devi
> > > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&am
> > > > > > > > > +p;da
> > > > > > > > > +ta=0
> > > > > > > > > +4%7C
> > > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4d850
> > > > > > > > > +8d92
> > > > > > > > > +f2da
> > > > > > > > > +0c0%
> > > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637592695286
> > > > > > > > > +8468
> > > > > > > > > +09%7
> > > > > > > > > +CUnk
> > > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLC
> > > > > > > > > +JBTi
> > > > > > > > > +I6Ik
> > > > > > > > > +1haW
> > > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrViQCc
> > > > > > > > > +rNtz
> > > > > > > > > +uDej
> > > > > > > > > +p8wo
> > > > > > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > > > > > +$schema:
> > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=http%
> > > > > > > > > +3A%2
> > > > > > > > > +F%2F
> > > > > > > > > +devi
> > > > > > > > > +cetree.org%2Fmeta-
> > > > > > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c0%7C
> > > > > > > > > +53d8
> > > > > > > > > +2571
> > > > > > > > > +da19
> > > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CUnkno
> > > > > > > > > +wn%7
> > > > > > > > > +CTWF
> > > > > > > > > +pbGZ
> > > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwi
> > > > > > > > > +LCJX
> > > > > > > > > +VCI6
> > > > > > > > > +Mn0%
> > > > > > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJgRIA
> > > > > > > > > +dLnh
> > > > > > > > > +Jraw
> > > > > > > > > +%3D&
> > > > > > > > > +amp;reserved=0
> > > > > >
> > > > > > *sigh*
> > > > > >
> > > > > > > > > +
> > > > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > > > +
> > > > > > > > > +maintainers:
> > > > > > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > +
> > > > > > > > > +allOf:
> > > > > > > > > + - $ref: "dma-controller.yaml#"
> > > > > > > > > +
> > > > > > > > > +properties:
> > > > > > > > > + compatible:
> > > > > > > > > + items:
> > > > > > > > > + - enum:
> > > > > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > > > > > >
> > > > > > > > Please use "renesas,r9a07g044-dmac".
> > > > > > >
> > > > > > > OK. Will change.
> > > > > > >
> > > > > > > > > + - const: renesas,rz-dmac
> > > > > > > >
> > > > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > > > >
> > > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested since I don't have the board.
> > > > > > > There is some difference in MID bit size. Other wise both identical.
> > > > > > >
> > > > > > > > > + renesas,rz-dmac-slavecfg:
> > > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > > > + description: |
> > > > > > > > > + DMA configuration for a slave channel. Each channel
> > > > > > > > > + must have an array of
> > > > > > > > > + 3 items as below.
> > > > > > > > > + first item in the array is MID+RID
> > > > > > > >
> > > > > > > > Already in dmas.
> > > > > > > >
> > > > > > > > > + second item in the array is slave src or dst
> > > > > > > > > + address
> > > > > > > >
> > > > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > > > >
> > > > > > > > > + third item in the array is channel configuration value.
> > > > > > > >
> > > > > > > > What exactly is this?
> > > > > >
> > > > > > What would prevent the DMA client from passing the configuration
> > > > > > to the DMA channel through the DMA engine API, just like it
> > > > > > passes the slave source or destination address ?
> > > > >
> > > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for both tx and rx.
> > > > > The only way we can distinguish it is from channel configuration value.
> > > >
> > > > Are those two different hardware DMA channels ? And configuration
> > > > values change between the two ?
> > >
> > > Yes, REQD is different, apart from this Rx have transfer source and Tx
> > > have Transfer destination.
> > > This particular SSIF ch2 is used only for half duplex compared to other
> > > SSIF channels.
> >
> > Does this mean there's a single DMA channel, used by two clients, but not
> > at the same time as it only supports half-duplex ?
>
> From hardware perspective, it is 2 channel. For eg:- playback/recording use case.
> You cannot do simultaneous playback, but you can do playback or record separately.
If the two channels have the same MID+RID and only differ by the
direction, I'd add a cell in the dmas property with the direction only.
The source/destination address should be dropped, as it's already known
by the driver.
This being said, in your example below, you have
dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
<&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
dma-names = "tx", "rx";
This looks like different MID+RID values for the two channels.
> > > > > > > > Does the R-Car DMAC have this too? If yes, how does its
> > > > > > > > driver handle it?
> > > > > > >
> > > > > > > On R-CAR DMAC, we have only MID + RID values. Where as here we
> > > > > > > have channel configuration value With different set of
> > > > > > > parameter as mentioned in Table 16.4.
> > > > > > >
> > > > > > > Please see Page 569, Table 16.4 On-Chip Module requests section.
> > > > > > >
> > > > > > > For eg:- as per Rob's suggestion, I have modelled the driver
> > > > > > > with the below entries in ALSA driver for playback/record use case.
> > > > > > >
> > > > > > > dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > > > <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > > > dma-names = "tx", "rx";
> > > > > > >
> > > > > > > Using first parameter, it gets dmac channel. using second and
> > > > > > > third parameter it configures the channel.
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
2021-06-14 17:30 ` Laurent Pinchart
@ 2021-06-15 8:06 ` Biju Das
0 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2021-06-15 8:06 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Geert Uytterhoeven, Vinod Koul, Rob Herring, Chris Brandt,
dmaengine,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Prabhakar Mahadev Lad, Linux-Renesas
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings
>
> Hi Biju,
>
> On Mon, Jun 14, 2021 at 04:33:03PM +0000, Biju Das wrote:
> > > On Mon, Jun 14, 2021 at 04:24:38PM +0000, Biju Das wrote:
> > > > > On Mon, Jun 14, 2021 at 04:09:04PM +0000, Biju Das wrote:
> > > > > > > On Mon, Jun 14, 2021 at 12:54:02PM +0000, Biju Das wrote:
> > > > > > > > > On Fri, Jun 11, 2021 at 1:36 PM Biju Das wrote:
> > > > > > > > > > Document RZ/G2L DMAC bindings.
> > > > > > > > > >
> > > > > > > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > > Reviewed-by: Lad Prabhakar
> > > > > > > > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > > > > > >
> > > > > > > > > Thanks for your patch!
> > > > > > > > >
> > > > > > > > > > --- /dev/null
> > > > > > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz
> > > > > > > > > > +++ -dma
> > > > > > > > > > +++ c.ya
> > > > > > > > > > +++ ml
> > > > > > > > > > @@ -0,0 +1,132 @@
> > > > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR
> > > > > > > > > > +BSD-2-Clause) %YAML
> > > > > > > > > > +1.2
> > > > > > > > > > +---
> > > > > > > > > > +$id:
> > > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=h
> > > > > > > > > > +ttp%
> > > > > > > > > > +3A%2
> > > > > > > > > > +F%2F
> > > > > > > > > > +devi
> > > > > > > > > > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%2
> > > > > > > > > > +3&am
> > > > > > > > > > +p;da
> > > > > > > > > > +ta=0
> > > > > > > > > > +4%7C
> > > > > > > > > > +01%7Cbiju.das.jz%40bp.renesas.com%7C4b547e10cbe64b6f4
> > > > > > > > > > +d850
> > > > > > > > > > +8d92
> > > > > > > > > > +f2da
> > > > > > > > > > +0c0%
> > > > > > > > > > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63759269
> > > > > > > > > > +5286
> > > > > > > > > > +8468
> > > > > > > > > > +09%7
> > > > > > > > > > +CUnk
> > > > > > > > > > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMz
> > > > > > > > > > +IiLC
> > > > > > > > > > +JBTi
> > > > > > > > > > +I6Ik
> > > > > > > > > > +1haW
> > > > > > > > > > +wiLCJXVCI6Mn0%3D%7C1000&sdata=5Jh%2FxPaia5ZOY0CrV
> > > > > > > > > > +iQCc
> > > > > > > > > > +rNtz
> > > > > > > > > > +uDej
> > > > > > > > > > +p8wo
> > > > > > > > > > +Nrx9iO0ht8%3D&reserved=0
> > > > > > > > > > +$schema:
> > > > > > > > > > +https://jpn01.safelinks.protection.outlook.com/?url=h
> > > > > > > > > > +ttp%
> > > > > > > > > > +3A%2
> > > > > > > > > > +F%2F
> > > > > > > > > > +devi
> > > > > > > > > > +cetree.org%2Fmeta-
> > > > > > > schemas%2Fcore.yaml%23&data=04%7C01%7Cbiju.das.
> > > > > > > > > > +jz%40bp.renesas.com%7C4b547e10cbe64b6f4d8508d92f2da0c
> > > > > > > > > > +0%7C
> > > > > > > > > > +53d8
> > > > > > > > > > +2571
> > > > > > > > > > +da19
> > > > > > > > > > +47e49cb4625a166a4a2a%7C0%7C0%7C637592695286846809%7CU
> > > > > > > > > > +nkno
> > > > > > > > > > +wn%7
> > > > > > > > > > +CTWF
> > > > > > > > > > +pbGZ
> > > > > > > > > > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1h
> > > > > > > > > > +aWwi
> > > > > > > > > > +LCJX
> > > > > > > > > > +VCI6
> > > > > > > > > > +Mn0%
> > > > > > > > > > +3D%7C1000&sdata=5qQ1PljM3e4Bn4%2FjdldYUHRBQL3jArJ
> > > > > > > > > > +gRIA
> > > > > > > > > > +dLnh
> > > > > > > > > > +Jraw
> > > > > > > > > > +%3D&
> > > > > > > > > > +amp;reserved=0
> > > > > > >
> > > > > > > *sigh*
> > > > > > >
> > > > > > > > > > +
> > > > > > > > > > +title: Renesas RZ/G2L DMA Controller
> > > > > > > > > > +
> > > > > > > > > > +maintainers:
> > > > > > > > > > + - Biju Das <biju.das.jz@bp.renesas.com>
> > > > > > > > > > +
> > > > > > > > > > +allOf:
> > > > > > > > > > + - $ref: "dma-controller.yaml#"
> > > > > > > > > > +
> > > > > > > > > > +properties:
> > > > > > > > > > + compatible:
> > > > > > > > > > + items:
> > > > > > > > > > + - enum:
> > > > > > > > > > + - renesas,dmac-r9a07g044 # RZ/G2{L,LC}
> > > > > > > > >
> > > > > > > > > Please use "renesas,r9a07g044-dmac".
> > > > > > > >
> > > > > > > > OK. Will change.
> > > > > > > >
> > > > > > > > > > + - const: renesas,rz-dmac
> > > > > > > > >
> > > > > > > > > Does this need many changes for RZ/A1H and RZ/A2M?
> > > > > > > >
> > > > > > > > It will work on both RZ/A1H and RZ/A2M. I have n't tested
> since I don't have the board.
> > > > > > > > There is some difference in MID bit size. Other wise both
> identical.
> > > > > > > >
> > > > > > > > > > + renesas,rz-dmac-slavecfg:
> > > > > > > > > > + $ref: /schemas/types.yaml#/definitions/uint32-array
> > > > > > > > > > + description: |
> > > > > > > > > > + DMA configuration for a slave channel. Each
> > > > > > > > > > + channel must have an array of
> > > > > > > > > > + 3 items as below.
> > > > > > > > > > + first item in the array is MID+RID
> > > > > > > > >
> > > > > > > > > Already in dmas.
> > > > > > > > >
> > > > > > > > > > + second item in the array is slave src or dst
> > > > > > > > > > + address
> > > > > > > > >
> > > > > > > > > As pointed out by Rob, already known by the slave driver.
> > > > > > > > >
> > > > > > > > > > + third item in the array is channel configuration
> value.
> > > > > > > > >
> > > > > > > > > What exactly is this?
> > > > > > >
> > > > > > > What would prevent the DMA client from passing the
> > > > > > > configuration to the DMA channel through the DMA engine API,
> > > > > > > just like it passes the slave source or destination address ?
> > > > > >
> > > > > > On RZ/G2L, there is 1 case(SSIF ch2) where MID+RID is same for
> both tx and rx.
> > > > > > The only way we can distinguish it is from channel configuration
> value.
> > > > >
> > > > > Are those two different hardware DMA channels ? And
> > > > > configuration values change between the two ?
> > > >
> > > > Yes, REQD is different, apart from this Rx have transfer source
> > > > and Tx have Transfer destination.
> > > > This particular SSIF ch2 is used only for half duplex compared to
> > > > other SSIF channels.
> > >
> > > Does this mean there's a single DMA channel, used by two clients,
> > > but not at the same time as it only supports half-duplex ?
> >
> > From hardware perspective, it is 2 channel. For eg:- playback/recording
> use case.
> > You cannot do simultaneous playback, but you can do playback or record
> separately.
>
> If the two channels have the same MID+RID and only differ by the
> direction, I'd add a cell in the dmas property with the direction only.
> The source/destination address should be dropped, as it's already known by
> the driver.
I have cross checked the manual again and it seems it is same DMA Tranfer request signal(ssif_dma_rt) for that
particular Dma client (SSIF ch2). So it is just one DMA. SO I will drop cell2 and cell3 and just use cell1 with
MID+RID values in next version.
> This being said, in your example below, you have
>
> dmas = <&dmac 0x255 0x10049c18 CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> <&dmac 0x256 0x10049c1c CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> dma-names = "tx", "rx";
>
> This looks like different MID+RID values for the two channels.
Yes, it is for SSIF ch0. Where it supports full duplex and it has DMA Tranfer request signal
ssif_dma_rx0 for receive and ssif_dma_tx0 for transmit.
Thanks,
Biju
>
> > > > > > > > > Does the R-Car DMAC have this too? If yes, how does its
> > > > > > > > > driver handle it?
> > > > > > > >
> > > > > > > > On R-CAR DMAC, we have only MID + RID values. Where as
> > > > > > > > here we have channel configuration value With different
> > > > > > > > set of parameter as mentioned in Table 16.4.
> > > > > > > >
> > > > > > > > Please see Page 569, Table 16.4 On-Chip Module requests
> section.
> > > > > > > >
> > > > > > > > For eg:- as per Rob's suggestion, I have modelled the
> > > > > > > > driver with the below entries in ALSA driver for
> playback/record use case.
> > > > > > > >
> > > > > > > > dmas = <&dmac 0x255 0x10049c18
> CH_CFG(0x1,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>,
> > > > > > > > <&dmac 0x256 0x10049c1c
> > > > > > > > CH_CFG(0x0,0x0,0x1,0x0,0x2,0x1,0x1,0x0)>;
> > > > > > > > dma-names = "tx", "rx";
> > > > > > > >
> > > > > > > > Using first parameter, it gets dmac channel. using second
> > > > > > > > and third parameter it configures the channel.
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
2021-06-11 11:36 ` [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
@ 2021-06-16 10:31 ` Vinod Koul
2021-06-16 11:02 ` Biju Das
0 siblings, 1 reply; 19+ messages in thread
From: Vinod Koul @ 2021-06-16 10:31 UTC (permalink / raw)
To: Biju Das
Cc: Lad Prabhakar, Chris Paterson, Geert Uytterhoeven, dmaengine,
Chris Brandt, linux-renesas-soc
On 11-06-21, 12:36, Biju Das wrote:
> Add DMA Controller driver for RZ/G2L SoC.
>
> Based on the work done by Chris Brandt for RZ/A DMA driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> drivers/dma/sh/Kconfig | 8 +
> drivers/dma/sh/Makefile | 1 +
> drivers/dma/sh/rz-dmac.c | 1050 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1059 insertions(+)
> create mode 100644 drivers/dma/sh/rz-dmac.c
>
> diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig
> index 13437323a85b..280a6d359e36 100644
> --- a/drivers/dma/sh/Kconfig
> +++ b/drivers/dma/sh/Kconfig
> @@ -47,3 +47,11 @@ config RENESAS_USB_DMAC
> help
> This driver supports the USB-DMA controller found in the Renesas
> SoCs.
> +
> +config RZ_DMAC
> + tristate "Renesas RZ/G2L Controller"
> + depends on ARCH_R9A07G044 || COMPILE_TEST
> + select RENESAS_DMA
> + help
> + This driver supports the general purpose DMA controller found in the
> + Renesas RZ/G2L SoC variants.
> diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile
> index 112fbd22bb3f..9b2927f543bf 100644
> --- a/drivers/dma/sh/Makefile
> +++ b/drivers/dma/sh/Makefile
> @@ -15,3 +15,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
>
> obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
> obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
> +obj-$(CONFIG_RZ_DMAC) += rz-dmac.o
> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
> new file mode 100644
> index 000000000000..87a902ba3cfa
> --- /dev/null
> +++ b/drivers/dma/sh/rz-dmac.c
> @@ -0,0 +1,1050 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Renesas RZ/G2L Controller Driver
> + *
> + * Based on imx-dma.c
> + *
> + * Copyright (C) 2021 Renesas Electronics Corp.
> + * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
> + * Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
> +#include <linux/interrupt.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_dma.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +#include <linux/spinlock.h>
> +
> +#include "../dmaengine.h"
> +
> +struct rz_dmac_slave_config {
> + u32 mid_rid;
> + dma_addr_t addr;
> + u32 chcfg;
> +};
why not use dma_slave_config()
> +
> +enum rz_dmac_prep_type {
> + RZ_DMAC_DESC_MEMCPY,
> + RZ_DMAC_DESC_SLAVE_SG,
> +};
> +
> +struct rz_lmdesc {
> + u32 header;
> + u32 sa;
> + u32 da;
> + u32 tb;
> + u32 chcfg;
> + u32 chitvl;
> + u32 chext;
> + u32 nxla;
> +};
> +
> +struct rz_dmac_desc {
> + struct list_head node;
what is this list node for?
> + struct dma_async_tx_descriptor desc;
> + enum dma_status status;
> + dma_addr_t src;
> + dma_addr_t dest;
> + size_t len;
> + enum dma_transfer_direction direction;
> + enum rz_dmac_prep_type type;
> + /* For memcpy */
> + unsigned int config_port;
> + unsigned int config_mem;
> + /* For slave sg */
> + struct scatterlist *sg;
> + unsigned int sgcount;
> +};
why not use virt_dma_desc ?
> +
> +struct rz_dmac_channel {
> + struct rz_dmac_engine *rzdma;
> + unsigned int index;
> + int irq;
> +
> + spinlock_t lock;
> + struct list_head ld_free;
> + struct list_head ld_queue;
> + struct list_head ld_active;
why not use virt_dma_chan() ?
> +
> + int descs_allocated;
> + enum dma_slave_buswidth word_size;
> + dma_addr_t per_address;
> + struct dma_chan chan;
> + struct dma_async_tx_descriptor desc;
> + enum dma_status status;
Both desc and chan need status?
> + const struct rz_dmac_slave_config *slave;
> + void __iomem *ch_base;
> + void __iomem *ch_cmn_base;
> +
> + struct {
> + struct rz_lmdesc *base;
> + struct rz_lmdesc *head;
> + struct rz_lmdesc *tail;
> + int valid;
> + dma_addr_t base_dma;
> + } lmdesc;
> +
> + u32 chcfg;
> + u32 chctrl;
> +
> + struct {
> + int issue;
> + int prep_slave_sg;
> + } stat;
> +};
I have glanced at the rest of the driver, looks mostly okay but please
move this to use virt_dma_chan and virt_dma_desc that would ease a lot
of code from driver
Thanks
--
~Vinod
^ permalink raw reply [flat|nested] 19+ messages in thread
* RE: [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
2021-06-16 10:31 ` Vinod Koul
@ 2021-06-16 11:02 ` Biju Das
0 siblings, 0 replies; 19+ messages in thread
From: Biju Das @ 2021-06-16 11:02 UTC (permalink / raw)
To: Vinod Koul
Cc: Prabhakar Mahadev Lad, Chris Paterson, Geert Uytterhoeven,
dmaengine, Chris Brandt, linux-renesas-soc
Hi Vinod,
Thanks for the feedback.
> Subject: Re: [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
>
> On 11-06-21, 12:36, Biju Das wrote:
> > Add DMA Controller driver for RZ/G2L SoC.
> >
> > Based on the work done by Chris Brandt for RZ/A DMA driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > drivers/dma/sh/Kconfig | 8 +
> > drivers/dma/sh/Makefile | 1 +
> > drivers/dma/sh/rz-dmac.c | 1050
> > ++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 1059 insertions(+)
> > create mode 100644 drivers/dma/sh/rz-dmac.c
> >
> > diff --git a/drivers/dma/sh/Kconfig b/drivers/dma/sh/Kconfig index
> > 13437323a85b..280a6d359e36 100644
> > --- a/drivers/dma/sh/Kconfig
> > +++ b/drivers/dma/sh/Kconfig
> > @@ -47,3 +47,11 @@ config RENESAS_USB_DMAC
> > help
> > This driver supports the USB-DMA controller found in the Renesas
> > SoCs.
> > +
> > +config RZ_DMAC
> > + tristate "Renesas RZ/G2L Controller"
> > + depends on ARCH_R9A07G044 || COMPILE_TEST
> > + select RENESAS_DMA
> > + help
> > + This driver supports the general purpose DMA controller found in
> the
> > + Renesas RZ/G2L SoC variants.
> > diff --git a/drivers/dma/sh/Makefile b/drivers/dma/sh/Makefile index
> > 112fbd22bb3f..9b2927f543bf 100644
> > --- a/drivers/dma/sh/Makefile
> > +++ b/drivers/dma/sh/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_SH_DMAE) += shdma.o
> >
> > obj-$(CONFIG_RCAR_DMAC) += rcar-dmac.o
> > obj-$(CONFIG_RENESAS_USB_DMAC) += usb-dmac.o
> > +obj-$(CONFIG_RZ_DMAC) += rz-dmac.o
> > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c new
> > file mode 100644 index 000000000000..87a902ba3cfa
> > --- /dev/null
> > +++ b/drivers/dma/sh/rz-dmac.c
> > @@ -0,0 +1,1050 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Renesas RZ/G2L Controller Driver
> > + *
> > + * Based on imx-dma.c
> > + *
> > + * Copyright (C) 2021 Renesas Electronics Corp.
> > + * Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
> > + * Copyright 2012 Javier Martin, Vista Silicon
> > +<javier.martin@vista-silicon.com> */
> > +
> > +#include <linux/dma-mapping.h>
> > +#include <linux/dmaengine.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/list.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_dma.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +#include <linux/spinlock.h>
> > +
> > +#include "../dmaengine.h"
> > +
> > +struct rz_dmac_slave_config {
> > + u32 mid_rid;
> > + dma_addr_t addr;
> > + u32 chcfg;
> > +};
>
> why not use dma_slave_config()
OK, will use dma_slav_config and remove this structure.
>
> > +
> > +enum rz_dmac_prep_type {
> > + RZ_DMAC_DESC_MEMCPY,
> > + RZ_DMAC_DESC_SLAVE_SG,
> > +};
> > +
> > +struct rz_lmdesc {
> > + u32 header;
> > + u32 sa;
> > + u32 da;
> > + u32 tb;
> > + u32 chcfg;
> > + u32 chitvl;
> > + u32 chext;
> > + u32 nxla;
> > +};
> > +
> > +struct rz_dmac_desc {
> > + struct list_head node;
>
> what is this list node for?
This node is for managing list descriptors.
>
> > + struct dma_async_tx_descriptor desc;
> > + enum dma_status status;
> > + dma_addr_t src;
> > + dma_addr_t dest;
> > + size_t len;
> > + enum dma_transfer_direction direction;
> > + enum rz_dmac_prep_type type;
> > + /* For memcpy */
> > + unsigned int config_port;
> > + unsigned int config_mem;
> > + /* For slave sg */
> > + struct scatterlist *sg;
> > + unsigned int sgcount;
> > +};
>
> why not use virt_dma_desc ?
OK. Will check with virt_dma_desc.
> > +
> > +struct rz_dmac_channel {
> > + struct rz_dmac_engine *rzdma;
> > + unsigned int index;
> > + int irq;
> > +
> > + spinlock_t lock;
> > + struct list_head ld_free;
> > + struct list_head ld_queue;
> > + struct list_head ld_active;
>
> why not use virt_dma_chan() ?
OK. Will check with virt_dma_chan
>
> > +
> > + int descs_allocated;
> > + enum dma_slave_buswidth word_size;
> > + dma_addr_t per_address;
> > + struct dma_chan chan;
> > + struct dma_async_tx_descriptor desc;
> > + enum dma_status status;
>
> Both desc and chan need status?
This status is unused. Will take it out.
>
> > + const struct rz_dmac_slave_config *slave;
> > + void __iomem *ch_base;
> > + void __iomem *ch_cmn_base;
> > +
> > + struct {
> > + struct rz_lmdesc *base;
> > + struct rz_lmdesc *head;
> > + struct rz_lmdesc *tail;
> > + int valid;
> > + dma_addr_t base_dma;
> > + } lmdesc;
> > +
> > + u32 chcfg;
> > + u32 chctrl;
> > +
> > + struct {
> > + int issue;
> > + int prep_slave_sg;
> > + } stat;
> > +};
>
> I have glanced at the rest of the driver, looks mostly okay but please
> move this to use virt_dma_chan and virt_dma_desc that would ease a lot of
> code from driver
OK, will check with virt_dma_chan and virt_dma_desc.
Regards,
Biju
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2021-06-16 11:02 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-06-11 11:36 [PATCH 0/5] Add RZ/G2L DMAC support Biju Das
2021-06-11 11:36 ` [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings Biju Das
2021-06-11 17:55 ` Rob Herring
2021-06-12 12:17 ` Biju Das
2021-06-11 19:39 ` Rob Herring
2021-06-12 12:26 ` Biju Das
2021-06-14 12:11 ` Geert Uytterhoeven
2021-06-14 12:54 ` Biju Das
2021-06-14 14:29 ` Laurent Pinchart
2021-06-14 16:09 ` Biju Das
2021-06-14 16:17 ` Laurent Pinchart
2021-06-14 16:24 ` Biju Das
2021-06-14 16:28 ` Laurent Pinchart
2021-06-14 16:33 ` Biju Das
2021-06-14 17:30 ` Laurent Pinchart
2021-06-15 8:06 ` Biju Das
2021-06-11 11:36 ` [PATCH 3/5] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
2021-06-16 10:31 ` Vinod Koul
2021-06-16 11:02 ` Biju Das
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