Re: [PATCH 0/3] dmaengine: dw-edma: Add support for native HDMA

From: Serge Semin <fancer.lancer@gmail.com>
To: Cai Huoqing <cai.huoqing@linux.dev>
Cc: caihuoqing <caihuoqing@baidu.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Vinod Koul <vkoul@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Serge Semin <Sergey.Semin@baikalelectronics.ru>,
	linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org
Subject: Re: [PATCH 0/3] dmaengine: dw-edma: Add support for native HDMA
Date: Fri, 10 Feb 2023 01:40:03 +0300	[thread overview]
Message-ID: <20230209224003.dkayfpzh2xkirloy@mobilestation> (raw)
In-Reply-To: <20220921064859.10328-1-cai.huoqing@linux.dev>

Hello Cai

On Wed, Sep 21, 2022 at 02:48:49PM +0800, Cai Huoqing wrote:
> From: caihuoqing <caihuoqing@baidu.com>
> 
> Add support for HDMA NATIVE, as long the IP design has set
> the compatible register map parameter-HDMA_NATIVE,
> which allows compatibility for native HDMA register configuration.
> 
> The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
> And the native HDMA registers are different from eDMA,
> so this patch add support for HDMA NATIVE mode.
> 
> HDMA write and read channels operate independently to maximize
> the performance of the HDMA read and write data transfer over
> the link When you configure the HDMA with multiple read channels,
> then it uses a round robin (RR) arbitration scheme to select
> the next read channel to be serviced.
> The same applies when you have multiple write channels.
> 
> The native HDMA driver also supports a maximum of 16 independent
> channels (8 write + 8 read), which can run simultaneously.
> Both SAR (Source Address Register) and DAR (Destination Address Register)
> are alignmented to byte.dmaengine: dw-edma: Add support for native HDMA
> 
> These series based on the series
> https://lore.kernel.org/dmaengine/20220822185332.26149-1-Sergey.Semin@baikalelectronics.ru/

My DW PCIe/eDMA series has been finally accepted by @Bjorn:
https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git/log/?h=pci/ctrl/dwc
(@Lorenzo, please note my changes in your pci/dwc are a bit outdated.)
The patchset will get into the mainline kernel on v6.3. So if you want
your series to go further you'll need either rebase your patches on the
@Bjorn's branch or wait for the kernel v6.3 release and rebase your work
on top of the latest kernel then. I'll provide some comments regarding
this patchset shortly.

-Serge(y)

> 
> Cai Huoqing (3):
>   dmaengine: dw-edma: Rename dw_edma_core_ops structure to
>     dw_edma_plat_ops
>   dmaengine: dw-edma: Create a new dw_edma_core_ops structure to
>     abstract controller operation
>   dmaengine: dw-edma: Add support for native HDMA
> 
>  drivers/dma/dw-edma/Makefile             |   6 +-
>  drivers/dma/dw-edma/dw-edma-core.c       |  65 ++---
>  drivers/dma/dw-edma/dw-edma-core.h       |  19 ++
>  drivers/dma/dw-edma/dw-edma-pcie.c       |   4 +-
>  drivers/dma/dw-edma/dw-edma-v0-core.c    |  90 ++++++-
>  drivers/dma/dw-edma/dw-edma-v0-core.h    |  14 +-
>  drivers/dma/dw-edma/dw-hdma-v0-core.c    | 304 +++++++++++++++++++++++
>  drivers/dma/dw-edma/dw-hdma-v0-core.h    |  17 ++
>  drivers/dma/dw-edma/dw-hdma-v0-debugfs.c | 150 +++++++++++
>  drivers/dma/dw-edma/dw-hdma-v0-debugfs.h |  22 ++
>  drivers/dma/dw-edma/dw-hdma-v0-regs.h    |  98 ++++++++
>  include/linux/dma/edma.h                 |   7 +-
>  12 files changed, 725 insertions(+), 71 deletions(-)
>  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.c
>  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-core.h
>  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.c
>  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-debugfs.h
>  create mode 100644 drivers/dma/dw-edma/dw-hdma-v0-regs.h
> 
> -- 
> 2.25.1
> 