Re: [PATCH 1/2] dmaengine: rcar-dmac: Don't set DMACHCLR bit 0 to 1 if iommu is mapped

[Geert Uytterhoeven <geert@linux-m68k.org>]

Hi Shimoda-san,

On Wed, Aug 28, 2019 at 1:15 PM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> The commit 20c169aceb45 ("dmaengine: rcar-dmac: clear pertinence
> number of channels") always set the DMACHCLR bit 0 to 1, but if
> iommu is mapped to the device, this driver doesn't need to clear it.
> So, this patch takes care of it by using "channels_mask" bitfield.

Thanks for your patch!

> Note that, this patch doesn't have a "Fixes:" tag because the driver
> doesn't manage the channel 0 anyway so that the behavior of
> the channel is not changed.

This patch does fix a bug, as GENMASK(dmac->n_channels - 1, 0) doesn't
take into account channels_offset.  Hence it not only clears channel 0,
as you mentioned, but also forgets to clear the last channel, which
is a real bug.

So I think this does warrant a
Fixes: 20c169aceb459575 ("dmaengine: rcar-dmac: clear pertinence
number of channels")

Or perhaps the actual bug should be fixed first in a separate patch?

> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

> --- a/drivers/dma/sh/rcar-dmac.c
> +++ b/drivers/dma/sh/rcar-dmac.c

> @@ -446,7 +448,7 @@ static int rcar_dmac_init(struct rcar_dmac *dmac)
>         u16 dmaor;
>
>         /* Clear all channels and enable the DMAC globally. */
> -       rcar_dmac_write(dmac, RCAR_DMACHCLR, GENMASK(dmac->n_channels - 1, 0));
> +       rcar_dmac_write(dmac, RCAR_DMACHCLR, dmac->channels_mask);
>         rcar_dmac_write(dmac, RCAR_DMAOR,
>                         RCAR_DMAOR_PRI_FIXED | RCAR_DMAOR_DME);
>
> @@ -822,6 +824,9 @@ static void rcar_dmac_stop_all_chan(struct rcar_dmac *dmac)
>         for (i = 0; i < dmac->n_channels; ++i) {
>                 struct rcar_dmac_chan *chan = &dmac->channels[i];
>
> +               if (!(dmac->channels_mask & BIT(i)))
> +                       continue;
> +
>                 /* Stop and reinitialize the channel. */
>                 spin_lock_irq(&chan->lock);
>                 rcar_dmac_chan_halt(chan);
> @@ -1801,6 +1806,8 @@ static int rcar_dmac_parse_of(struct device *dev, struct rcar_dmac *dmac)
>                 return -EINVAL;
>         }
>
> +       dmac->channels_mask = GENMASK(dmac->n_channels - 1, 0);

You're aware dmac->n_channels can be 99, as per the check above, jut out of
context? ;-)

Probably that check should be changed to reject >= 32, as the hardware
and driver don't support more than 32 bits in CHCLR anyway.
> +
>         return 0;
>  }
>
> @@ -1810,7 +1817,6 @@ static int rcar_dmac_probe(struct platform_device *pdev)
>                 DMA_SLAVE_BUSWIDTH_2_BYTES | DMA_SLAVE_BUSWIDTH_4_BYTES |
>                 DMA_SLAVE_BUSWIDTH_8_BYTES | DMA_SLAVE_BUSWIDTH_16_BYTES |
>                 DMA_SLAVE_BUSWIDTH_32_BYTES | DMA_SLAVE_BUSWIDTH_64_BYTES;
> -       unsigned int channels_offset = 0;
>         struct dma_device *engine;
>         struct rcar_dmac *dmac;
>         const struct rcar_dmac_of_data *data;
> @@ -1843,10 +1849,8 @@ static int rcar_dmac_probe(struct platform_device *pdev)
>          * level we can't disable it selectively, so ignore channel 0 for now if
>          * the device is part of an IOMMU group.
>          */
> -       if (device_iommu_mapped(&pdev->dev)) {
> -               dmac->n_channels--;
> -               channels_offset = 1;
> -       }
> +       if (device_iommu_mapped(&pdev->dev))
> +               dmac->channels_mask &= ~BIT(0);
>
>         dmac->channels = devm_kcalloc(&pdev->dev, dmac->n_channels,
>                                       sizeof(*dmac->channels), GFP_KERNEL);

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds