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Wed, 11 Dec 2019 14:46:07 +0000 From: Radhey Shyam Pandey To: Vinod Koul CC: "dan.j.williams@intel.com" , Michal Simek , "nick.graumann@gmail.com" , "andrea.merello@gmail.com" , Appana Durga Kedareswara Rao , "mcgrof@kernel.org" , "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , git Subject: RE: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all Thread-Topic: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_all Thread-Index: AQHVo1uM5nn5YHd560C/NFUjbNUe6Key97yAgAIaTxA= Date: Wed, 11 Dec 2019 14:46:06 +0000 Message-ID: References: <1574664121-13451-1-git-send-email-radhey.shyam.pandey@xilinx.com> <20191210060113.GP82508@vkoul-mobl> In-Reply-To: <20191210060113.GP82508@vkoul-mobl> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=radheys@xilinx.com; x-originating-ip: [149.199.50.133] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: ef0dec40-0481-4d15-5cd0-08d77e48daea x-ms-traffictypediagnostic: CH2PR02MB6039:|CH2PR02MB6039: x-ld-processed: 657af505-d5df-48d0-8300-c31994686c5c,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:3513; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef0dec40-0481-4d15-5cd0-08d77e48daea X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Dec 2019 14:46:06.9820 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: C/y7fQpR/hiFMEAHvZue0wZq0viLsZsFdSRQSo6+6vqeIwqOvEafgGsAnvQDbV8hVNJTAcWegITq5NwGaSOk1w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6039 Sender: dmaengine-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org > -----Original Message----- > From: Vinod Koul > Sent: Tuesday, December 10, 2019 11:31 AM > To: Radhey Shyam Pandey > Cc: dan.j.williams@intel.com; Michal Simek ; > nick.graumann@gmail.com; andrea.merello@gmail.com; Appana Durga > Kedareswara Rao ; mcgrof@kernel.org; > dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; git > > Subject: Re: [PATCH] dmaengine: xilinx_dma: Reset DMA channel in > dma_terminate_all >=20 > On 25-11-19, 12:12, Radhey Shyam Pandey wrote: > > Reset DMA channel after stop to ensure that pending transfers and > > FIFOs in the datapath are flushed or completed. It fixes intermittent > > data verification failure reported by xilinx dma test client. > > > > Signed-off-by: Radhey Shyam Pandey > > --- > > drivers/dma/xilinx/xilinx_dma.c | 17 +++++++++-------- > > 1 file changed, 9 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/dma/xilinx/xilinx_dma.c > > b/drivers/dma/xilinx/xilinx_dma.c index a9c5d5c..6f1539c 100644 > > --- a/drivers/dma/xilinx/xilinx_dma.c > > +++ b/drivers/dma/xilinx/xilinx_dma.c > > @@ -2404,16 +2404,17 @@ static int xilinx_dma_terminate_all(struct > dma_chan *dchan) > > u32 reg; > > int err; > > > > - if (chan->cyclic) > > - xilinx_dma_chan_reset(chan); >=20 > So reset is required for non cyclic cases as well now? Yes. In absence of reset in non-cyclic case, when dmatest client driver is stressed and loaded/unloaded multiple times we see dma=20 data comparison failures. Possibly IP is prefetching/holding the previous state and reset ensures a clean state on each iteration. >=20 > > - > > - err =3D chan->stop_transfer(chan); > > - if (err) { > > - dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > - chan, dma_ctrl_read(chan, > XILINX_DMA_REG_DMASR)); > > - chan->err =3D true; > > + if (!chan->cyclic) { > > + err =3D chan->stop_transfer(chan); >=20 > no stop for cyclic now..? After reset stop is not needed, so for the cyclic mode we only do reset. >=20 > > + if (err) { > > + dev_err(chan->dev, "Cannot stop channel %p: %x\n", > > + chan, dma_ctrl_read(chan, > > + XILINX_DMA_REG_DMASR)); > > + chan->err =3D true; > > + } > > } > > > > + xilinx_dma_chan_reset(chan); > > /* Remove and free all of the descriptors in the lists */ > > xilinx_dma_free_descriptors(chan); > > chan->idle =3D true; > > -- > > 2.7.4 >=20 > -- > ~Vinod