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Wed, 11 Nov 2020 02:35:25 +0000 Received: from MWHPR11MB1645.namprd11.prod.outlook.com ([fe80::7ccb:c84d:5042:b50e]) by MWHPR11MB1645.namprd11.prod.outlook.com ([fe80::7ccb:c84d:5042:b50e%10]) with mapi id 15.20.3541.025; Wed, 11 Nov 2020 02:35:25 +0000 From: "Tian, Kevin" To: Jason Gunthorpe , "Raj, Ashok" CC: Thomas Gleixner , "Williams, Dan J" , "Jiang, Dave" , "Bjorn Helgaas" , "vkoul@kernel.org" , "Dey, Megha" , "maz@kernel.org" , "bhelgaas@google.com" , "alex.williamson@redhat.com" , "Pan, Jacob jun" , "Liu, Yi L" , "Lu, Baolu" , "Kumar, Sanjay K" , "Luck, Tony" , "kwankhede@nvidia.com" , "eric.auger@redhat.com" , "parav@mellanox.com" , "rafael@kernel.org" , "netanelg@mellanox.com" , "shahafs@mellanox.com" , "yan.y.zhao@linux.intel.com" , "pbonzini@redhat.com" , "Ortiz, Samuel" , "Hossain, Mona" , "dmaengine@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pci@vger.kernel.org" , "kvm@vger.kernel.org" Subject: RE: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection Thread-Topic: [PATCH v4 06/17] PCI: add SIOV and IMS capability detection Thread-Index: AQHWru26nCdjGLbk80+ZhPfx8iZ806mwjmaAgAAYm4CAABfkAIAAARAAgAQYdwCAAOAGcIAAp6mAgAD1diCAAJvfgIAADi9AgAAGfICAArW6cIAAY8KAgAA79QCAABGDgIAAY1IAgAAHBYCAAsnwAIAAVwYAgAC+sACAAGcnAIAAVyaAgABtcgCAAJg3AIAAy40Q Date: Wed, 11 Nov 2020 02:35:25 +0000 Message-ID: References: <20201106164850.GA85879@otc-nc-03> <20201106175131.GW2620339@nvidia.com> <20201107001207.GA2620339@nvidia.com> <87pn4nk7nn.fsf@nanos.tec.linutronix.de> <20201108235852.GC32074@araj-mobl1.jf.intel.com> <874klykc7h.fsf@nanos.tec.linutronix.de> <20201109173034.GG2620339@nvidia.com> <87pn4mi23u.fsf@nanos.tec.linutronix.de> <20201110051412.GA20147@otc-nc-03> <20201110141900.GO2620339@nvidia.com> In-Reply-To: <20201110141900.GO2620339@nvidia.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: nvidia.com; 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x-ms-exchange-antispam-messagedata: 9f4X22qoU1Wop6+EOuKIUGIXk6IwgqGbl0VNJ4I6N1sXc5RsWDLPkd2sx3b8HyliNDBSoLGjyeNxowFoHCjPQCv4W77T1dAozt6C/fPECoKb98Q8Or5XKJ8/53WEtgsZlALtfc35OG7ui60QiT9YdQ4Dm1fvv0yJi/qwv17vwntA2co0+3ZsESXVpBXRcRhy56e6vGzymiIK75H7cFIDvyj0bCVRnIbYz93OsimfDsdZMjDUfDcs59XLXCTohlmmbvm6yFeM2d0rrNsbmFE9Pmtl8YbvxR3KrItBr/w6XZdkMgtFaNdF/f+nDq0QD9SPKcx4uBYFhd0Ja/gyCWdq1MAWCNE3JxrMkm4o+TFcSxwuJ/WXP5dA3wPEAo75DN5Ahm4JzTQVPjEm+F6U/htWzX8UEmVKWL9ebpMOzGvxDXZPDWQ6KjurvXm3lLxd6/hLoKqdMEhO62otuqS8YdztT1O8PXBjck7vDkcXmsFG3J/ggCoR8xb8JskYU0lVHi5ruJO3PpdlZwU+i0PzqF9uVVv2Ok+P6viDU8TE8i4tv+lyqomsluxl4UNNb8MlJ0xFZjf2AqsSB7zVuEOdPRJ8gFmIDNvSlI0e6BV4AxekUPV5QVPkkHALejL8Zv+Lssl6I+ZF9wUm9yecrnJJI+Y49A== Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR11MB1645.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9d73c8ce-1e9e-4632-9657-08d885ea7200 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2020 02:35:25.2848 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jCKT3OZv4n5jA6bc+feHyuGMVmTC+jD6eQ3azJB4u7bIftHSk6//i6z1gmggQL1cBcxrIYJ4ZUPO8l6GJzstLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1247 X-OriginatorOrg: intel.com Precedence: bulk List-ID: X-Mailing-List: dmaengine@vger.kernel.org > From: Jason Gunthorpe > Sent: Tuesday, November 10, 2020 10:19 PM > On Mon, Nov 09, 2020 at 09:14:12PM -0800, Raj, Ashok wrote: >=20 > > was used for interrupt message storage (on the wire they follow the > > same format), and also to ensure interoperability of devices > > supporting IMS across CPU vendors (who may not support PASID TLP > > prefix). This is one reason that led to interrupts from IMS to not > > use PASID (and match the wire format of MSI/MSI-X generated > > interrupts). The other problem was disambiguation between DMA to > > SVM v/s interrupts. >=20 > This is a defect in the IOMMU, not something fundamental. >=20 > The IOMMU needs to know if the interrupt range is active or not for > each PASID. Process based SVA will, of course, not enable interrupts > on the PASID, VM Guest based PASID will. >=20 Unfortunately it's more than that. The interrupt message is firstly recogni= zed at root complex today and then routed to the IOMMU, unlike other DMA requests. I'm not saying it's an unsolvable limitation, but just wants to p= oint out that to achieve such goal there are more things to be considered beyond= =20 the IOMMU. Thanks Kevin