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From: Biju Das <biju.das.jz@bp.renesas.com>
To: Vinod Koul <vkoul@kernel.org>
Cc: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	Chris Paterson <Chris.Paterson2@renesas.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	"dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
	Chris Brandt <Chris.Brandt@renesas.com>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>
Subject: RE: [PATCH v4 2/4] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC
Date: Tue, 27 Jul 2021 13:45:11 +0000	[thread overview]
Message-ID: <OS0PR01MB59224844C17A1EE620E2D18786E99@OS0PR01MB5922.jpnprd01.prod.outlook.com> (raw)
In-Reply-To: <YP/+r4HzCaAZbUWh@matsya>

Hi Vinod,

Thanks for the feedback.

> Subject: Re: [PATCH v4 2/4] drivers: dma: sh: Add DMAC driver for RZ/G2L
> SoC
> 
> On 19-07-21, 10:25, Biju Das wrote:
> 
> > +struct rz_dmac_chan {
> > +	struct virt_dma_chan vc;
> > +	void __iomem *ch_base;
> > +	void __iomem *ch_cmn_base;
> > +	unsigned int index;
> > +	int irq;
> > +	struct rz_dmac_desc *desc;
> > +	int descs_allocated;
> > +
> > +	enum dma_slave_buswidth src_word_size;
> > +	enum dma_slave_buswidth dst_word_size;
> > +	dma_addr_t src_per_address;
> > +	dma_addr_t dst_per_address;
> > +
> > +	u32 chcfg;
> > +	u32 chctrl;
> > +	int mid_rid;
> > +
> > +	struct list_head ld_free;
> > +	struct list_head ld_queue;
> > +	struct list_head ld_active;
> > +
> > +	struct {
> > +		struct rz_lmdesc *base;
> > +		struct rz_lmdesc *head;
> > +		struct rz_lmdesc *tail;
> > +		int valid;
> > +		dma_addr_t base_dma;
> > +	} lmdesc;
> 
> should this be not part of rz_dmac_desc than channel?

No. It is channel specific. A channel has 64 HW legacy descriptors(see rz_dmac_chan_probe function) and 16 rz_dmac_desc( see rz_dmac_chan_resources function)

> > +static int rz_dmac_config(struct dma_chan *chan,
> > +			  struct dma_slave_config *config) {
> > +	struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
> > +	u32 *ch_cfg;
> > +
> > +	channel->src_per_address = config->src_addr;
> > +	channel->src_word_size = config->src_addr_width;
> > +	channel->dst_per_address = config->dst_addr;
> > +	channel->dst_word_size = config->dst_addr_width;
> > +
> > +	if (config->peripheral_config) {
> > +		ch_cfg = config->peripheral_config;
> > +		channel->chcfg = *ch_cfg;
> > +	}
> 
> can you explain what this the ch_cfg here and what does it represent?

It is a 32 bit value represent channel config value which supplied by each client driver during slave config.
It contains information like transfer mode,src/destination data size, Ack mode, Level type, DMA request on rising edge or falling
Edge, request direction etc...

For eg:- The channel config for SSI tx is (0x11228).
An example usage can be found here [1]

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20210719134040.7964-8-biju.das.jz@bp.renesas.com/

Regards,
Biju


> 
> --
> ~Vinod

  reply	other threads:[~2021-07-27 13:45 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-19  9:25 [PATCH v4 0/4] Add RZ/G2L DMAC support Biju Das
2021-07-19  9:25 ` [PATCH v4 2/4] drivers: dma: sh: Add DMAC driver for RZ/G2L SoC Biju Das
2021-07-27  7:56   ` Biju Das
2021-07-27 12:40   ` Vinod Koul
2021-07-27 13:45     ` Biju Das [this message]
2021-07-28  6:20       ` Vinod Koul
2021-07-28  7:00         ` Biju Das
2021-07-28 11:05           ` Vinod Koul
2021-07-28 11:58             ` Biju Das
2021-07-28 12:34               ` Geert Uytterhoeven
2021-07-28 12:42                 ` Biju Das

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