RE: [PATCH v2 1/4] dt-bindings: dma: Document RZ/G2L bindings

[Biju Das <biju.das.jz@bp.renesas.com>]

Hi Rob,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/4] dt-bindings: dma: Document RZ/G2L bindings
> 
> On Mon, Jun 21, 2021 at 03:33:36PM +0100, Biju Das wrote:
> > Document RZ/G2L DMAC bindings.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > Note:-  This patch has dependency on #include
> > <dt-bindings/clock/r9a07g044-cpg.h> file which will be in next 5.14-rc1
> release.
> >
> > v2->v3:
> >   * Added error interrupt first.
> >   * Updated clock and reset maxitems.
> >   * Added Geert's Rb tag.
> > v1->v2:
> >   * Made interrupt names in defined order
> >   * Removed src address and channel configuration from dma-cells.
> >   * Changed the compatibele string to "renesas,r9a07g044-dmac".
> > v1:-
> >   *
> > https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
> > hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F2021061111364
> > 2.18457-2-biju.das.jz%40bp.renesas.com%2F&amp;data=04%7C01%7Cbiju.das.
> > jz%40bp.renesas.com%7C148e8caa6dad418a945f08d935b63b07%7C53d82571da194
> > 7e49cb4625a166a4a2a%7C0%7C0%7C637599879065585493%7CUnknown%7CTWFpbGZsb
> > 3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%
> > 7C1000&amp;sdata=oMUg74TGAm%2BNelP1na314IdJojqHY0TGvr01y7i0HlA%3D&amp;
> > reserved=0
> > ---
> >  .../bindings/dma/renesas,rz-dmac.yaml         | 120 ++++++++++++++++++
> >  1 file changed, 120 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > new file mode 100644
> > index 000000000000..0a59907ed041
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > @@ -0,0 +1,120 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fschemas%2Fdma%2Frenesas%2Crz-dmac.yaml%23&amp;data=04%7C
> > +01%7Cbiju.das.jz%40bp.renesas.com%7C148e8caa6dad418a945f08d935b63b07%
> > +7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637599879065585493%7CUnk
> > +nown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> > +wiLCJXVCI6Mn0%3D%7C1000&amp;sdata=V3tJCTBjLjFfR1Hm%2F3hU64jrgSL1qvXoj
> > +e%2FeBPBCjy4%3D&amp;reserved=0
> > +$schema:
> > +https://jpn01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> > +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&amp;data=04%7C01%7Cbiju.das.
> > +jz%40bp.renesas.com%7C148e8caa6dad418a945f08d935b63b07%7C53d82571da19
> > +47e49cb4625a166a4a2a%7C0%7C0%7C637599879065585493%7CUnknown%7CTWFpbGZ
> > +sb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%
> > +3D%7C1000&amp;sdata=FPhQ7PGQlnhj%2B%2BNJ%2BSCJvbOMXlYXUbaacEfBKib80KU
> > +%3D&amp;reserved=0
> > +
> > +title: Renesas RZ/G2L DMA Controller
> > +
> > +maintainers:
> > +  - Biju Das <biju.das.jz@bp.renesas.com>
> > +
> > +allOf:
> > +  - $ref: "dma-controller.yaml#"
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
> > +      - const: renesas,rz-dmac
> > +
> > +  reg:
> > +    items:
> > +      - description: Control and channel register block
> > +      - description: DMA extended resource selector block
> > +
> > +  interrupts:
> > +    maxItems: 17
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: error
> > +      - const: ch0
> > +      - const: ch1
> > +      - const: ch2
> > +      - const: ch3
> > +      - const: ch4
> > +      - const: ch5
> > +      - const: ch6
> > +      - const: ch7
> > +      - const: ch8
> > +      - const: ch9
> > +      - const: ch10
> > +      - const: ch11
> > +      - const: ch12
> > +      - const: ch13
> > +      - const: ch14
> > +      - const: ch15
> > +
> > +  clocks:
> > +    maxItems: 2
> 
> Need to define what each one is.

OK, will describe the clock items.

> > +
> > +  '#dma-cells':
> > +    const: 1
> > +    description:
> > +      The cell specifies the MID/RID of the DMAC port connected to
> > +      the DMA client.
> > +
> > +  dma-channels:
> > +    const: 16
> > +
> > +  power-domains:
> > +    maxItems: 1
> > +
> > +  resets:
> > +    maxItems: 2

OK, will describe the reset items.

Regards,
Biju

> 
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +  - interrupt-names
> > +  - clocks
> > +  - '#dma-cells'
> > +  - dma-channels
> > +  - power-domains
> > +  - resets
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> > +
> > +    dmac: dma-controller@11820000 {
> > +        compatible = "renesas,r9a07g044-dmac",
> > +                     "renesas,rz-dmac";
> > +        reg = <0x11820000 0x10000>,
> > +              <0x11830000 0x10000>;
> > +        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> > +                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
> > +        interrupt-names = "error",
> > +                          "ch0", "ch1", "ch2", "ch3",
> > +                          "ch4", "ch5", "ch6", "ch7",
> > +                          "ch8", "ch9", "ch10", "ch11",
> > +                          "ch12", "ch13", "ch14", "ch15";
> > +        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
> > +                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
> > +        power-domains = <&cpg>;
> > +        resets = <&cpg R9A07G044_DMAC_ACLK>,
> > +                 <&cpg R9A07G044_DMAC_PCLK>;
> > +        #dma-cells = <1>;
> > +        dma-channels = <16>;
> > +    };
> > --
> > 2.17.1
> >
> >